I use bbl as the coreboot's payload, bbl can start and running into the enter_supervisor_mode function, but can't continue.
I added some code to print register state before mret and print memory on target address. I debugged it for a long time and didn't know where the problem was. hoping to get your help.
Below is my output:
```
mhartid : 2 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008cec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000
mhartid : 1 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008bec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000
mhartid : 3 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008dec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000
mhartid : 4 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008eec0 mepc : 0000000080280000 mcause : 0000000000000001 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : ffffffe000927c74 sscratch : 0000000000000000 sepc : 0000000080282240 scause : 0000000000000003 sip : 0000000000000200 satp : 0000000000000000
0000000080280000: 73 10 40 10 97 31 d3 00 0000000080280008: 93 81 c1 8d 99 62 73 b0 0000000080280010: 02 10 93 86 01 16 05 46 0000000080280018: af a6 c6 00 d9 ee 2a 84 0000000080280020: ae 84 17 01 d0 00 13 01 0000000080280028: e1 fd ef 20 00 1f ef 00 0000000080280030: 80 02 17 62 d0 00 13 02 0000000080280038: e2 a8 23 24 82 02 17 e1 0000000080280040: cf 00 13 01 21 fc 09 65 0000000080280048: 2a 91 22 85 a6 85 ef 20 0000000080280050: 80 27 6f 00 40 68 9b 05 0000000080280058: f0 ff 93 95 55 02 17 05 0000000080280060: 00 00 13 05 25 fa 89 8d 0000000080280068: ae 90 17 05 00 00 13 05 0000000080280070: 65 03 2e 95 73 10 55 10 0000000080280078: 17 56 db 00 13 06 86 f8 ```
------------------
王翔
安全研究员
广州市腾御安信息科技有限公司
广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024
Hi,
On Mon, Dec 10, 2018 at 05:29:44PM +0800, 王翔 wrote:
I use bbl as the coreboot's payload, bbl can start and running into the enter_supervisor_mode function, but can't continue.
I added some code to print register state before mret and print memory on target address. I debugged it for a long time and didn't know where the problem was. hoping to get your help.
Below is my output:
mhartid : 2
[...]
mhartid : 1
[...]
mhartid : 3
[...]
mhartid : 4
[...]
My first guess is that BBL is waiting for Hart 0, but I have not looked at BBL's code to verify that this could be the case.
Jonathan
This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code. So there is no status information for hart0.
------------------
王翔
安全研究员
广州市腾御安信息科技有限公司
广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024
This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
------------------ Original ------------------This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
From: "Jonathan Neuschäfer"j.neuschaefer@gmx.net;This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not supThis is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code. port S-Mode and cannot run kernel code.This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
Date: Mon, Dec 10, 2018 07:16 PMThis is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
To: "王翔"merle@tya.email; Cc: "coreboot"coreboot@coreboot.org; "j.neuschaefer"j.neuschaefer@gmx.net; "philipp"philipp@hug.cx; "citypw"citypw@gmail.com; This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
Subject: Re: The problem of coreboot porting to fu540
Hi,
On Mon, Dec 10, 2018 at 05:29:44PM +0800, 王翔 wrote:This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code. This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernThis is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code. el code.
I use bbl as the coreboot's payload, bbl can start and running into the enter_supervisor_mode function, but can't continue. This is the code used to exits M-Mode. hart0 was paused before , because hart0 does not support S-Mode and cannot run kernel code.
I added some code to print register state before mret and print memory on target address. I debugged it for a long time and didn't know where the problem was. hoping to get your help.
Below is my output:
mhartid : 2
[...]
mhartid : 1
[...]
mhartid : 3
[...]
mhartid : 4
[...]
My first guess is that BBL is waiting for Hart 0, but I have not looked at BBL's code to verify that this could be the case.
Jonathan
-
Jonathan Neuschäfer -
王翔