Re: [coreboot] MRC in coreboot

[Aaron Durbin]

cbmem timstamps will be needed.

Looks like FSP is manipulating the tsc:

BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0

I have a hard time believing that took 4291 seconds.

On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V <
[e-mail]> wrote:
> Hi Aaron,
>
> PFA the console log for your reference.
>
> Please look into this and provide feedback.
>
> Thanks,
> Antony
>
> -----Original Message-----
> From: Aaron Durbin [mailto:[e-mail]]
> Sent: Thursday, October 11, 2018 7:27 PM
> To: Antony AbeePrakash X V 
> Cc: Coreboot ; Dinesh Kumar <
> [e-mail]>
> Subject: Re: [coreboot] MRC in coreboot
>
> On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <
> [e-mail]> wrote:
> > Hi All,
> >
> > We are able to achieve the memory initialization time reduction. Now we
>
> have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf
> boot).
> > We have reduced the unwanted codes. We would like to reduce the boot
>
> time to less than 2sec.
> > Could anyone please tell what can be done further ?
>
> You're going to need to post more information (cbmem timings and console
> logs).
> > Thanks,
> > Antony
> >
> > -----Original Message-----
> > From: Aaron Durbin [mailto:[e-mail]]
> > Sent: Wednesday, September 05, 2018 7:39 PM
> > To: Antony AbeePrakash X V 
> > Cc: Coreboot 
> > Subject: Re: [coreboot] MRC in coreboot
> >
> > On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <
>
> [e-mail]> wrote:
> > > Hi,
> > >
> > > We are developing coreboot for Apollo lake custom board.  MRC training
>
> data save is enabled in FSP using Binary configuration tool.
> > > But we are getting logs like,
> > >
> > > No MRC cache found.
> > >
> > > MRC SeCUmaSize memory size from SeC ... 0
> > >
> > > MRC Parameters not valid. Status is Success
> > >
> > > MRC:CpuMemoryTest Successful!
> > >
> > > Saving MRC data using CSE through HECI interface
> >
> > I have never seen this path used in coreboot. This line above is saying
>
> CSE is responsible for saving and retrieving training data. In coreboot we
> use the main processor to save and restore. I suggest reading over the UPD
> parameters and ensure they match with our typical use cases. BCT tool
> enabling 'training data save' sounds like it's enabling CSE path.
> > > Try to find MRC training data HOB.
> > >
> > > No MRC training data found, perform data save via HECI.
> > >
> > > Saved MRC training data with status (0x80000003)
> > >
> > > It seems that MRC data is not found and saved. Also I found that there
>
> are options to add MRC file path and mrc.bin in menuconfig. The only option
> I have is save cached MRC settings.
> > > What this mrc.bin will do?
> > >
> > > How to add the mrc.bin in coreboot?
> > >
> > > Please explain on this.
> > >
> > > Thanks & Regards,
> > >
> > > Antony
> > >
> > > L&T Technology Services Ltd
> > >
> > > www.LntTechservices.com
> > >
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> > >
> >
> > L&T Technology Services Ltd
> >
> > www.LntTechservices.comhttp://www.lnttechservices.com/
> >
> > This Email may contain confidential or privileged information for the
>
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> L&T Technology Services Ltd
>
> www.LntTechservices.comhttp://www.lnttechservices.com/
>
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> intended recipient (s). If you are not the intended recipient, please do
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