[PATCH] flashrom: restructure SPI support, part 3

[Carl-Daniel Hailfinger]

flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-spirestructure/flash.h
===================================================================
--- flashrom-spirestructure/flash.h	(Revision 3302)
+++ flashrom-spirestructure/flash.h	(Arbeitskopie)
@@ -360,6 +360,11 @@
 int spi_chip_erase_c7(struct flashchip *flash);
 int spi_chip_write(struct flashchip *flash, uint8_t *buf);
 int spi_chip_read(struct flashchip *flash, uint8_t *buf);
+uint8_t spi_read_status_register();
+void spi_disable_blockprotect(void);
+void spi_byte_program(int address, uint8_t byte);
+void spi_page_program(int block, uint8_t *buf, uint8_t *bios);
+void spi_nbyte_read(int address, uint8_t *bytes, int len);

/* 82802ab.c */
 int probe_82802ab(struct flashchip *flash);
@@ -371,6 +376,13 @@
 int erase_29f040b(struct flashchip *flash);
 int write_29f040b(struct flashchip *flash, uint8_t *buf);

+/* it87spi.c */
+extern uint16_t it8716f_flashport;
+int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
+int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
+int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
+void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios);
+
 /* jedec.c */
 void toggle_ready_jedec(volatile uint8_t *dst);
 void data_polling_jedec(volatile uint8_t *dst, uint8_t data);
Index: flashrom-spirestructure/spi.c
===================================================================
--- flashrom-spirestructure/spi.c	(Revision 3302)
+++ flashrom-spirestructure/spi.c	(Arbeitskopie)
@@ -2,7 +2,6 @@
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
- * Copyright (C) 2008 Ronald Hoogenboom 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,159 +28,9 @@
 #include "flash.h"
 #include "spi.h"

-#define ITE_SUPERIO_PORT1	0x2e
-#define ITE_SUPERIO_PORT2	0x4e

-
-uint16_t it8716f_flashport = 0;
-/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
-int fast_spi = 1;
-
 void spi_prettyprint_status_register(struct flashchip *flash);
-void spi_disable_blockprotect(void);

-/* Generic Super I/O helper functions */
-uint8_t regval(uint16_t port, uint8_t reg)
-{
-	outb(reg, port);
-	return inb(port + 1);
-}
-
-void regwrite(uint16_t port, uint8_t reg, uint8_t val)
-{
-	outb(reg, port);
-	outb(val, port + 1);
-}
-
-/* Helper functions for most recent ITE IT87xx Super I/O chips */
-#define CHIP_ID_BYTE1_REG	0x20
-#define CHIP_ID_BYTE2_REG	0x21
-static void enter_conf_mode_ite(uint16_t port)
-{
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	if (port == ITE_SUPERIO_PORT1)
-		outb(0x55, port);
-	else
-		outb(0xaa, port);
-}
-
-static void exit_conf_mode_ite(uint16_t port)
-{
-	regwrite(port, 0x02, 0x02);
-}
-
-static uint16_t find_ite_spi_flash_port(uint16_t port)
-{
-	uint8_t tmp = 0;
-	uint16_t id, flashport = 0;
-
-	enter_conf_mode_ite(port);
-
-	id = regval(port, CHIP_ID_BYTE1_REG) << 8;
-	id |= regval(port, CHIP_ID_BYTE2_REG);
-
-	/* TODO: Handle more IT87xx if they support flash translation */
-	if (id == 0x8716) {
-		/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
-		tmp = regval(port, 0x24) & 0xFE;
-		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
-			0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
-		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
-			0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
-		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
-			0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
-		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
-			0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
-		printf("LPC write to serial flash %sabled\n",
-			(tmp & 1 << 4) ? "en" : "dis");
-		printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
-		/* LDN 0x7, reg 0x64/0x65 */
-		regwrite(port, 0x07, 0x7);
-		flashport = regval(port, 0x64) << 8;
-		flashport |= regval(port, 0x65);
-	}
-	exit_conf_mode_ite(port);
-	return flashport;
-}
-
-int it87xx_probe_spi_flash(const char *name)
-{
-	it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
-	if (!it8716f_flashport)
-		it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
-	return (!it8716f_flashport);
-}
-
-/* The IT8716F only supports commands with length 1,2,4,5 bytes including
-   command byte and can not read more than 3 bytes from the device.
-   This function expects writearr[0] to be the first byte sent to the device,
-   whereas the IT8716F splits commands internally into address and non-address
-   commands with the address in inverse wire order. That's why the register
-   ordering in case 4 and 5 may seem strange. */
-static int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
-{
-	uint8_t busy, writeenc;
-	int i;
-
-	do {
-		busy = inb(it8716f_flashport) & 0x80;
-	} while (busy);
-	if (readcnt > 3) {
-		printf("%s called with unsupported readcnt %i.\n",
-			__FUNCTION__, readcnt);
-		return 1;
-	}
-	switch (writecnt) {
-	case 1:
-		outb(writearr[0], it8716f_flashport + 1);
-		writeenc = 0x0;
-		break;
-	case 2:
-		outb(writearr[0], it8716f_flashport + 1);
-		outb(writearr[1], it8716f_flashport + 7);
-		writeenc = 0x1;
-		break;
-	case 4:
-		outb(writearr[0], it8716f_flashport + 1);
-		outb(writearr[1], it8716f_flashport + 4);
-		outb(writearr[2], it8716f_flashport + 3);
-		outb(writearr[3], it8716f_flashport + 2);
-		writeenc = 0x2;
-		break;
-	case 5:
-		outb(writearr[0], it8716f_flashport + 1);
-		outb(writearr[1], it8716f_flashport + 4);
-		outb(writearr[2], it8716f_flashport + 3);
-		outb(writearr[3], it8716f_flashport + 2);
-		outb(writearr[4], it8716f_flashport + 7);
-		writeenc = 0x3;
-		break;
-	default:
-		printf("%s called with unsupported writecnt %i.\n",
-			__FUNCTION__, writecnt);
-		return 1;
-	}
-	/* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
-	 * Note:
-	 * We can't use writecnt directly, but have to use a strange encoding.
-	 */ 
-	outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
-
-	if (readcnt > 0) {
-		do {
-			busy = inb(it8716f_flashport) & 0x80;
-		} while (busy);
-
-		for (i = 0; i < readcnt; i++) {
-			readarr[i] = inb(it8716f_flashport + 5 + i);
-		}
-	}
-
-	return 0;
-}
-
 int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
 {
    if (it8716f_flashport)
@@ -390,28 +239,13 @@
    return 0;
 }

-/* Page size is usually 256 bytes */
-void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
-	int i;
-
-	spi_write_enable();
-	outb(0x06 , it8716f_flashport + 1);
-	outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
-	for (i = 0; i < 256; i++) {
-		bios[256 * block + i] = buf[256 * block + i];
-	}
-	outb(0, it8716f_flashport);
-	/* Wait until the Write-In-Progress bit is cleared.
-	 * This usually takes 1-10 ms, so wait in 1 ms steps.
-	 */
-	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-		usleep(1000);
-}
-
 void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
 {
-	if (it8716f_flashport)
+	if (it8716f_flashport) {
    	it8716f_spi_page_program(block, buf, bios);
+		return;
+	}
+	printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
 }

/*
@@ -452,30 +286,8 @@
    }
 }

-/*
- * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
- * Program chip using firmware cycle byte programming. (SLOW!)
- */
-int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf)
+void spi_nbyte_read(int address, uint8_t *bytes, int len)
 {
-	int total_size = 1024 * flash->total_size;
-	int i;
-	fast_spi = 0;
-
-	spi_disable_blockprotect();
-	for (i = 0; i < total_size; i++) {
-		spi_write_enable();
-		spi_byte_program(i, buf[i]);
-		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
-			myusec_delay(10);
-	}
-	/* resume normal ops... */
-	outb(0x20, it8716f_flashport);
-	return 0;
-}
-
-void spi_3byte_read(int address, uint8_t *bytes, int len)
-{
    const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
    	(address >> 16) & 0xff,
    	(address >> 8) & 0xff,
@@ -486,39 +298,19 @@
    spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes);
 }

-/*
- * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
- * Need to read this big flash using firmware cycles 3 byte at a time.
- */
 int spi_chip_read(struct flashchip *flash, uint8_t *buf)
 {
-	int total_size = 1024 * flash->total_size;
-	int i;
-	fast_spi = 0;
-
-	if (total_size > 512 * 1024) {
-		for (i = 0; i < total_size; i += 3) {
-			int toread = 3;
-			if (total_size - i < toread)
-				toread = total_size - i;
-			spi_3byte_read(i, buf + i, toread);
-		}
-	} else {
-		memcpy(buf, (const char *)flash->virtual_memory, total_size);
-	}
-	return 0;
+	if (it8716f_flashport)
+		return it8716f_spi_chip_read(flash, buf);
+	printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
+	return 1;
 }

-int spi_chip_write(struct flashchip *flash, uint8_t *buf) {
-	int total_size = 1024 * flash->total_size;
-	int i;
-	if (total_size > 512 * 1024) {
-		it8716f_over512k_spi_chip_write(flash, buf);
-	} else {
-		for (i = 0; i < total_size / 256; i++) {
-			spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
-		}
-	}
-	return 0;
+int spi_chip_write(struct flashchip *flash, uint8_t *buf)
+{
+	if (it8716f_flashport)
+		return it8716f_spi_chip_write(flash, buf);
+	printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
+	return 1;
 }

Index: flashrom-spirestructure/Makefile
===================================================================
--- flashrom-spirestructure/Makefile	(Revision 3302)
+++ flashrom-spirestructure/Makefile	(Arbeitskopie)
@@ -24,7 +24,7 @@
    sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \
    w49f002u.o 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o \
    sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \
-	flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o
+	flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o

all: pciutils dep $(PROGRAM)

Index: flashrom-spirestructure/it87spi.c
===================================================================
--- /dev/null	2007-09-21 23:50:58.000000000 +0200
+++ flashrom-spirestructure/it87spi.c	2008-05-13 17:19:55.000000000 +0200
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
+ * Copyright (C) 2008 Ronald Hoogenboom 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Contains the ITE IT87* SPI specific routines
+ */
+
+#include <stdio.h>
+#include <pci/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include "flash.h"
+#include "spi.h"
+
+#define ITE_SUPERIO_PORT1	0x2e
+#define ITE_SUPERIO_PORT2	0x4e
+
+
+uint16_t it8716f_flashport = 0;
+/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
+int fast_spi = 1;
+
+/* Generic Super I/O helper functions */
+uint8_t regval(uint16_t port, uint8_t reg)
+{
+	outb(reg, port);
+	return inb(port + 1);
+}
+
+void regwrite(uint16_t port, uint8_t reg, uint8_t val)
+{
+	outb(reg, port);
+	outb(val, port + 1);
+}
+
+/* Helper functions for most recent ITE IT87xx Super I/O chips */
+#define CHIP_ID_BYTE1_REG	0x20
+#define CHIP_ID_BYTE2_REG	0x21
+static void enter_conf_mode_ite(uint16_t port)
+{
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	if (port == ITE_SUPERIO_PORT1)
+		outb(0x55, port);
+	else
+		outb(0xaa, port);
+}
+
+static void exit_conf_mode_ite(uint16_t port)
+{
+	regwrite(port, 0x02, 0x02);
+}
+
+static uint16_t find_ite_spi_flash_port(uint16_t port)
+{
+	uint8_t tmp = 0;
+	uint16_t id, flashport = 0;
+
+	enter_conf_mode_ite(port);
+
+	id = regval(port, CHIP_ID_BYTE1_REG) << 8;
+	id |= regval(port, CHIP_ID_BYTE2_REG);
+
+	/* TODO: Handle more IT87xx if they support flash translation */
+	if (id == 0x8716) {
+		/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
+		tmp = regval(port, 0x24) & 0xFE;
+		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
+			0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
+		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
+			0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
+		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
+			0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
+		printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
+			0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
+		printf("LPC write to serial flash %sabled\n",
+			(tmp & 1 << 4) ? "en" : "dis");
+		printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
+		/* LDN 0x7, reg 0x64/0x65 */
+		regwrite(port, 0x07, 0x7);
+		flashport = regval(port, 0x64) << 8;
+		flashport |= regval(port, 0x65);
+	}
+	exit_conf_mode_ite(port);
+	return flashport;
+}
+
+int it87xx_probe_spi_flash(const char *name)
+{
+	it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
+	if (!it8716f_flashport)
+		it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
+	return (!it8716f_flashport);
+}
+
+/* The IT8716F only supports commands with length 1,2,4,5 bytes including
+   command byte and can not read more than 3 bytes from the device.
+   This function expects writearr[0] to be the first byte sent to the device,
+   whereas the IT8716F splits commands internally into address and non-address
+   commands with the address in inverse wire order. That's why the register
+   ordering in case 4 and 5 may seem strange. */
+int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
+{
+	uint8_t busy, writeenc;
+	int i;
+
+	do {
+		busy = inb(it8716f_flashport) & 0x80;
+	} while (busy);
+	if (readcnt > 3) {
+		printf("%s called with unsupported readcnt %i.\n",
+			__FUNCTION__, readcnt);
+		return 1;
+	}
+	switch (writecnt) {
+	case 1:
+		outb(writearr[0], it8716f_flashport + 1);
+		writeenc = 0x0;
+		break;
+	case 2:
+		outb(writearr[0], it8716f_flashport + 1);
+		outb(writearr[1], it8716f_flashport + 7);
+		writeenc = 0x1;
+		break;
+	case 4:
+		outb(writearr[0], it8716f_flashport + 1);
+		outb(writearr[1], it8716f_flashport + 4);
+		outb(writearr[2], it8716f_flashport + 3);
+		outb(writearr[3], it8716f_flashport + 2);
+		writeenc = 0x2;
+		break;
+	case 5:
+		outb(writearr[0], it8716f_flashport + 1);
+		outb(writearr[1], it8716f_flashport + 4);
+		outb(writearr[2], it8716f_flashport + 3);
+		outb(writearr[3], it8716f_flashport + 2);
+		outb(writearr[4], it8716f_flashport + 7);
+		writeenc = 0x3;
+		break;
+	default:
+		printf("%s called with unsupported writecnt %i.\n",
+			__FUNCTION__, writecnt);
+		return 1;
+	}
+	/* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
+	 * Note:
+	 * We can't use writecnt directly, but have to use a strange encoding.
+	 */ 
+	outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
+
+	if (readcnt > 0) {
+		do {
+			busy = inb(it8716f_flashport) & 0x80;
+		} while (busy);
+
+		for (i = 0; i < readcnt; i++) {
+			readarr[i] = inb(it8716f_flashport + 5 + i);
+		}
+	}
+
+	return 0;
+}
+
+/* Page size is usually 256 bytes */
+void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
+	int i;
+
+	spi_write_enable();
+	outb(0x06 , it8716f_flashport + 1);
+	outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
+	for (i = 0; i < 256; i++) {
+		bios[256 * block + i] = buf[256 * block + i];
+	}
+	outb(0, it8716f_flashport);
+	/* Wait until the Write-In-Progress bit is cleared.
+	 * This usually takes 1-10 ms, so wait in 1 ms steps.
+	 */
+	while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+		usleep(1000);
+}
+
+/*
+ * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
+ * Program chip using firmware cycle byte programming. (SLOW!)
+ */
+int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf)
+{
+	int total_size = 1024 * flash->total_size;
+	int i;
+	fast_spi = 0;
+
+	spi_disable_blockprotect();
+	for (i = 0; i < total_size; i++) {
+		spi_write_enable();
+		spi_byte_program(i, buf[i]);
+		while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+			myusec_delay(10);
+	}
+	/* resume normal ops... */
+	outb(0x20, it8716f_flashport);
+	return 0;
+}
+
+/*
+ * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
+ * Need to read this big flash using firmware cycles 3 byte at a time.
+ */
+int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf)
+{
+	int total_size = 1024 * flash->total_size;
+	int i;
+	fast_spi = 0;
+
+	if (total_size > 512 * 1024) {
+		for (i = 0; i < total_size; i += 3) {
+			int toread = 3;
+			if (total_size - i < toread)
+				toread = total_size - i;
+			spi_nbyte_read(i, buf + i, toread);
+		}
+	} else {
+		memcpy(buf, (const char *)flash->virtual_memory, total_size);
+	}
+	return 0;
+}
+
+int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf) {
+	int total_size = 1024 * flash->total_size;
+	int i;
+	if (total_size > 512 * 1024) {
+		it8716f_over512k_spi_chip_write(flash, buf);
+	} else {
+		for (i = 0; i < total_size / 256; i++) {
+			spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
+		}
+	}
+	return 0;
+}
+

[Ward Vandewege]

On Tue, May 13, 2008 at 05:33:44PM +0200, Carl-Daniel Hailfinger wrote:
> flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
> file it87spi.c.
> No behavioural changes, but greatly improved SPI abstraction.

Hmm. I have a hardware-modded board with 2 chips and a switch. The mod might
be a bit flakey, I see odd stuff sometimes (it will erase both chips
regardless of position of switch, but it always only programs the right
chip). So the fact that flashrom sees 2 chips might be an artifact of that
problem, but maybe not...

Switch in position 1:

# ./flashrom -m m57sli -V
Calibrating delay loop... 697M loops per second. OK.
Found canidate at: 00000530-00000eb8
Found coreboot table at 0x00000530.
Coreboot table found at 0xb7d54530.
Coreboot header(24) checksum: 2c03 table(2440) checksum: 38ac entries: 27
Vendor ID: GIGABYTE, part ID: m57sli
Overwritten by command line, vendor ID: (null), part ID: m57sli.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash
segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for Macronix MX25L3205, 4096 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix MX25L4005, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Chip status register is 00
Chip status register: Status Register Write Disable (SRWD) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
MX25L4005 found at physical address 0xfff80000.
Probing for Macronix MX25L8005, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x92, id2 0xe4
Probing for PMC Pm25LV010, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV016B, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV020, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV040, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV080B, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV512, 64 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff
Probing for Spansion S25FL016A, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST25VF016B, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST25VF040B, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xe9, id2 0x0
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x12, id2 0x17
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P10-A, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P128, 16384 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P16, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P20, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P32, 4096 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P40, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P64, 8192 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P80, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W25x10, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x20, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x40, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x80, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0xff, id2 0xff
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did
0xff
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid
0x49, did 0x4d
Probing for EON unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
unknown SPI chip found at physical address 0x0.
Probing for PMC unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Multiple flash chips were detected: MX25L4005 unknown SPI chip
Please specify which chip to use with the -c <chipname> option.

---------------------------------------------------------------------

And after flipping the switch:

---------------------------------------------------------------------

# ./flashrom -m m57sli -V
Calibrating delay loop... 697M loops per second. OK.
Found canidate at: 00000530-00000eb8
Found coreboot table at 0x00000530.
Coreboot table found at 0xb7d76530.
Coreboot header(24) checksum: 2c03 table(2440) checksum: 38ac entries: 27
Vendor ID: GIGABYTE, part ID: m57sli
Overwritten by command line, vendor ID: (null), part ID: m57sli.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash
segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x4c
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x7f, id2 0x45
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for Macronix MX25L3205, 4096 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX25L4005, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX25L8005, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x7f, id2 0x45
Probing for PMC Pm25LV010, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV016B, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV020, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV040, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV080B, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV512, 64 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff
Probing for Spansion S25FL016A, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST SST25VF016B, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Chip status register is 1c
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is set
Chip status register: Bit 3 / Block Protect 1 (BP1) is set
Chip status register: Bit 2 / Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Resulting block protection : all
SST25VF016B found at physical address 0xffe00000.
Probing for SST SST25VF040B, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x7f, id2 0x45
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xe1, id2 0xff
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x6c, id2 0x6e
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x7f, id2 0x45
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P10-A, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P128, 16384 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P16, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P20, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P32, 4096 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P40, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P64, 8192 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P80, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x4c
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x7f2d, id2 0x45
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x7f2d, id2 0x45
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x7f, id2 0x45
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W25x10, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x20, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x40, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x80, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0x7a, id2 0xc2
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did
0xff
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid
0x7f, did 0x45
Probing for EON unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
unknown SPI chip found at physical address 0x0.
Probing for ST unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Multiple flash chips were detected: SST25VF016B unknown SPI chip
Please specify which chip to use with the -c <chipname> option.

---------------------------------------------------------------------

Well, looks like you are right, no behavioural changes, this is an unpatched
r3303:

# ./flashrom -m m57sli -V
Calibrating delay loop... 712M loops per second. OK.
Found canidate at: 00000530-00000eb8
Found coreboot table at 0x00000530.
Coreboot table found at 0xb7cba530.
Coreboot header(24) checksum: 2c03 table(2440) checksum: 38ac entries: 27
Vendor ID: GIGABYTE, part ID: m57sli
Overwritten by command line, vendor ID: (null), part ID: m57sli.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash
segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for Macronix MX25L3205, 4096 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix MX25L4005, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Chip status register is 00
Chip status register: Status Register Write Disable (SRWD) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
MX25L4005 found at physical address 0xfff80000.
Probing for Macronix MX25L8005, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x92, id2 0xe4
Probing for PMC Pm25LV010, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV016B, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV020, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV040, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV080B, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm25LV512, 64 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff
Probing for Spansion S25FL016A, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST25VF016B, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST25VF040B, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xe9, id2 0x0
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x12, id2 0x17
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P10-A, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P128, 16384 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P16, 2048 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P20, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P32, 4096 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P40, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P64, 8192 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M25P80, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x49, id2 0x4d
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W25x10, 128 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x20, 256 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x40, 512 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W25x80, 1024 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0xff, id2 0xff
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x49, id2 0x4d
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x92, id2 0xe4
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did
0xff
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid
0x49, did 0x4d
Probing for EON unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for Macronix unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
unknown SPI chip found at physical address 0x0.
Probing for PMC unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for SST unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Probing for ST unknown SPI chip, 0 KB: RDID returned c2 20 13.
probe_spi: id1 0xc2, id2 0x2013
Multiple flash chips were detected: MX25L4005 unknown SPI chip
Please specify which chip to use with the -c <chipname> option.

---------------------------------------------------------------------

And after flipping the switch:

---------------------------------------------------------------------

d# ./flashrom -m m57sli -V 
Calibrating delay loop... 736M loops per second. OK.
Found canidate at: 00000530-00000eb8
Found coreboot table at 0x00000530.
Coreboot table found at 0xb7d5e530.
Coreboot header(24) checksum: 2c03 table(2440) checksum: 38ac entries: 27
Vendor ID: GIGABYTE, part ID: m57sli
Overwritten by command line, vendor ID: (null), part ID: m57sli.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash
segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x4c
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x7f, id2 0x45
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for Macronix MX25L3205, 4096 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX25L4005, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX25L8005, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0x7f, id2 0x45
Probing for PMC Pm25LV010, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV016B, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV020, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV040, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV080B, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm25LV512, 64 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff
Probing for Spansion S25FL016A, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST SST25VF016B, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Chip status register is 1c
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is set
Chip status register: Bit 3 / Block Protect 1 (BP1) is set
Chip status register: Bit 2 / Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Resulting block protection : all
SST25VF016B found at physical address 0xffe00000.
Probing for SST SST25VF040B, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x7f, id2 0x45
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xe1, id2 0xff
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x6c, id2 0x6e
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x7f, id2 0x45
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff
Probing for ST M25P05-A, 64 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P10-A, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P128, 16384 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P16, 2048 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P20, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P32, 4096 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P40, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P64, 8192 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M25P80, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x45
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x7f, id2 0x4c
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x7f2d, id2 0x45
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x7f2d, id2 0x45
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x7f, id2 0x45
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W25x10, 128 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x20, 256 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x40, 512 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W25x80, 1024 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x7a, id2 0xc2
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0x7a, id2 0xc2
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0x7f2d, id2 0x45
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did
0xff
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid
0x7f, did 0x45
Probing for EON unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for Macronix unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for PMC unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Probing for SST unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
unknown SPI chip found at physical address 0x0.
Probing for ST unknown SPI chip, 0 KB: RDID returned bf 25 41.
probe_spi: id1 0xbf, id2 0x2541
Multiple flash chips were detected: SST25VF016B unknown SPI chip
Please specify which chip to use with the -c <chipname> option.

Thanks,
Ward.

[Carl-Daniel Hailfinger]

On 14.05.2008 00:01, Ward Vandewege wrote:
> On Tue, May 13, 2008 at 05:33:44PM +0200, Carl-Daniel Hailfinger wrote:
> > flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
> > file it87spi.c.
> > No behavioural changes, but greatly improved SPI abstraction.
>
> Hmm. I have a hardware-modded board with 2 chips and a switch. The mod might
> be a bit flakey, I see odd stuff sometimes (it will erase both chips
> regardless of position of switch, but it always only programs the right
> chip). So the fact that flashrom sees 2 chips might be an artifact of that
> problem, but maybe not...

Yes, that problem was introduced with r3291.
> Switch in position 1:
>
> # ./flashrom -m m57sli -V
> Probing for Macronix MX25L4005, 512 KB: RDID returned c2 20 13.
> probe_spi: id1 0xc2, id2 0x2013
> Chip status register is 00
> Chip status register: Status Register Write Disable (SRWD) is not set
> Chip status register: Bit 6 is not set
> Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
> Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
> Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
> Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
> Chip status register: Write Enable Latch (WEL) is not set
> Chip status register: Write In Progress (WIP/BUSY) is not set
> MX25L4005 found at physical address 0xfff80000.
> [...]
> Probing for Macronix unknown SPI chip, 0 KB: RDID returned c2 20 13.
> probe_spi: id1 0xc2, id2 0x2013
> unknown SPI chip found at physical address 0x0.
> [...]
> Multiple flash chips were detected: MX25L4005 unknown SPI chip
> Please specify which chip to use with the -c <chipname> option.
>
> And after flipping the switch:
>
> # ./flashrom -m m57sli -V
> Probing for SST SST25VF016B, 2048 KB: RDID returned bf 25 41.
> probe_spi: id1 0xbf, id2 0x2541
> Chip status register is 1c
> Chip status register: Block Protect Write Disable (BPL) is not set
> Chip status register: Auto Address Increment Programming (AAI) is not set
> Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
> Chip status register: Bit 4 / Block Protect 2 (BP2) is set
> Chip status register: Bit 3 / Block Protect 1 (BP1) is set
> Chip status register: Bit 2 / Block Protect 0 (BP0) is set
> Chip status register: Write Enable Latch (WEL) is not set
> Chip status register: Write In Progress (WIP/BUSY) is not set
> Resulting block protection : all
> SST25VF016B found at physical address 0xffe00000.
> [...]
> Probing for SST unknown SPI chip, 0 KB: RDID returned bf 25 41.
> probe_spi: id1 0xbf, id2 0x2541
> unknown SPI chip found at physical address 0x0.
> [...]
> Multiple flash chips were detected: SST25VF016B unknown SPI chip
> Please specify which chip to use with the -c <chipname> option.
>
> Well, looks like you are right, no behavioural changes, this is an unpatched
> r3303:

Good. Can you ack the change after testing wth flashrom -c $FLASHCHIP?

Regards,
Carl-Daniel

[Peter Stuge]

On Tue, May 13, 2008 at 06:01:12PM -0400, Ward Vandewege wrote:
> Hmm. I have a hardware-modded board with 2 chips and a switch. The
> mod might be a bit flakey, I see odd stuff sometimes (it will erase
> both chips regardless of position of switch, but it always only
> programs the right chip).

To make switching more reliable I suggest a different mod;

Populate R89 and R130 as before with 100k resistors but also populate
Q4 and Q5 with BC847 transistors, R86 and R389 with 100k resistors
and R90 and R91 with 10k resistors. Then short Q2-2 and Q2-3 together
and short Q43-2 and Q43-3 together. Finally, the switch center goes
to VCC, and the two outer switch connections go to the south end of
R86 and R389. (The ends facing away from the flash chips.)

I have tested this with several meters of cable to the switch without
issues.

This works better because the high-speed CS# signal stays in the
Q4 and Q5 transistors on the mainboard, making the mod much less
sensitive to interference.
> So the fact that flashrom sees 2 chips might be an artifact of that
> problem, but maybe not...

It is not.
> Switch in position 1:
>
> # ./flashrom -m m57sli -V

..
> Multiple flash chips were detected: MX25L4005 unknown SPI chip
> And after flipping the switch:
>
> # ./flashrom -m m57sli -V

..
> Multiple flash chips were detected: SST25VF016B unknown SPI chip
> Well, looks like you are right, no behavioural changes, this is an
> unpatched r3303:

Yes. This was introduced with the code that looks for multiple flash
chips.

We should remove those unknown flash chip entries and have a
different user interface to do what they did.

The probe function will always find the unknown flash chips. A
temporary kludge is to not allow them to be detected other than as
the first flash chip that is found.

//Peter

[Peter Stuge]

On Tue, May 13, 2008 at 05:33:44PM +0200, Carl-Daniel Hailfinger wrote:
> flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
> file it87spi.c.
> No behavioural changes, but greatly improved SPI abstraction.
>
> Signed-off-by: Carl-Daniel Hailfinger

I'm good with this! Have not tested though.

Acked-by: Peter Stuge
> Index: flashrom-spirestructure/flash.h
>
> --- flashrom-spirestructure/flash.h	(Revision 3302)
> +++ flashrom-spirestructure/flash.h	(Arbeitskopie)
> @@ -360,6 +360,11 @@
>  int spi_chip_erase_c7(struct flashchip *flash);
>  int spi_chip_write(struct flashchip *flash, uint8_t *buf);
>  int spi_chip_read(struct flashchip *flash, uint8_t *buf);
> +uint8_t spi_read_status_register();
> +void spi_disable_blockprotect(void);
> +void spi_byte_program(int address, uint8_t byte);
> +void spi_page_program(int block, uint8_t *buf, uint8_t *bios);
> +void spi_nbyte_read(int address, uint8_t *bytes, int len);
>
> /* 82802ab.c */
>  int probe_82802ab(struct flashchip *flash);
> @@ -371,6 +376,13 @@
>  int erase_29f040b(struct flashchip *flash);
>  int write_29f040b(struct flashchip *flash, uint8_t *buf);
>
> +/* it87spi.c */
> +extern uint16_t it8716f_flashport;
> +int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
> +int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
> +int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
> +void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios);
>
> /* jedec.c */
>  void toggle_ready_jedec(volatile uint8_t *dst);
>  void data_polling_jedec(volatile uint8_t *dst, uint8_t data);
> Index: flashrom-spirestructure/spi.c
> ===================================================================
> --- flashrom-spirestructure/spi.c	(Revision 3302)
> +++ flashrom-spirestructure/spi.c	(Arbeitskopie)
> @@ -2,7 +2,6 @@
> This file is part of the flashrom project.
> Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
> Copyright (C) 2008 Ronald Hoogenboom
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
>
> @@ -29,159 +28,9 @@
>  #include "flash.h"
>  #include "spi.h"
>
> -#define ITE_SUPERIO_PORT1	0x2e
> -#define ITE_SUPERIO_PORT2	0x4e
>
> -uint16_t it8716f_flashport = 0;
> -/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
> -int fast_spi = 1;
>
> void spi_prettyprint_status_register(struct flashchip *flash);
> -void spi_disable_blockprotect(void);
>
> -/* Generic Super I/O helper functions */
> -uint8_t regval(uint16_t port, uint8_t reg)
> -{
> outb(reg, port);
> return inb(port + 1);
>
> -}
>
> -void regwrite(uint16_t port, uint8_t reg, uint8_t val)
> -{
> outb(reg, port);
> outb(val, port + 1);
>
> -}
>
> -/* Helper functions for most recent ITE IT87xx Super I/O chips */
> -#define CHIP_ID_BYTE1_REG	0x20
> -#define CHIP_ID_BYTE2_REG	0x21
> -static void enter_conf_mode_ite(uint16_t port)
> -{
> outb(0x87, port);
> outb(0x01, port);
> outb(0x55, port);
> if (port == ITE_SUPERIO_PORT1)
> outb(0x55, port);
> else
> outb(0xaa, port);
>
> -}
>
> -static void exit_conf_mode_ite(uint16_t port)
> -{
> regwrite(port, 0x02, 0x02);
>
> -}
>
> -static uint16_t find_ite_spi_flash_port(uint16_t port)
> -{
> uint8_t tmp = 0;
> uint16_t id, flashport = 0;
> enter_conf_mode_ite(port);
> id = regval(port, CHIP_ID_BYTE1_REG) << 8;
> id |= regval(port, CHIP_ID_BYTE2_REG);
> /* TODO: Handle more IT87xx if they support flash translation */
> if (id == 0x8716) {
> /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
> tmp = regval(port, 0x24) & 0xFE;
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
> printf("LPC write to serial flash %sabled\n",
> 	(tmp & 1 << 4) ? "en" : "dis");
> printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
> /* LDN 0x7, reg 0x64/0x65 */
> regwrite(port, 0x07, 0x7);
> flashport = regval(port, 0x64) << 8;
> flashport |= regval(port, 0x65);
> }
> exit_conf_mode_ite(port);
> return flashport;
>
> -}
>
> -int it87xx_probe_spi_flash(const char *name)
> -{
> it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
> if (!it8716f_flashport)
> it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
> return (!it8716f_flashport);
>
> -}
>
> -/* The IT8716F only supports commands with length 1,2,4,5 bytes including
> command byte and can not read more than 3 bytes from the device.
> This function expects writearr[0] to be the first byte sent to the device,
> whereas the IT8716F splits commands internally into address and non-address
> commands with the address in inverse wire order. That's why the register
> ordering in case 4 and 5 may seem strange. */
>
> -static int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
> -{
> uint8_t busy, writeenc;
> int i;
> do {
> busy = inb(it8716f_flashport) & 0x80;
> } while (busy);
> if (readcnt > 3) {
> printf("%s called with unsupported readcnt %i.\n",
> 	__FUNCTION__, readcnt);
> return 1;
> }
> switch (writecnt) {
> case 1:
> outb(writearr[0], it8716f_flashport + 1);
> writeenc = 0x0;
> break;
> case 2:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 7);
> writeenc = 0x1;
> break;
> case 4:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 4);
> outb(writearr[2], it8716f_flashport + 3);
> outb(writearr[3], it8716f_flashport + 2);
> writeenc = 0x2;
> break;
> case 5:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 4);
> outb(writearr[2], it8716f_flashport + 3);
> outb(writearr[3], it8716f_flashport + 2);
> outb(writearr[4], it8716f_flashport + 7);
> writeenc = 0x3;
> break;
> default:
> printf("%s called with unsupported writecnt %i.\n",
> 	__FUNCTION__, writecnt);
> return 1;
> }
> /* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
> * Note:
> * We can't use writecnt directly, but have to use a strange encoding.
> */ 
> outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
> if (readcnt > 0) {
> do {
> 	busy = inb(it8716f_flashport) & 0x80;
> } while (busy);
> for (i = 0; i < readcnt; i++) {
> 	readarr[i] = inb(it8716f_flashport + 5 + i);
> }
> }
> return 0;
>
> -}
>
> int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
>  {
>    if (it8716f_flashport)
> @@ -390,28 +239,13 @@
>    return 0;
>  }
>
> -/* Page size is usually 256 bytes */
> -void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
> int i;
> spi_write_enable();
> outb(0x06 , it8716f_flashport + 1);
> outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
> for (i = 0; i < 256; i++) {
> bios[256 * block + i] = buf[256 * block + i];
> }
> outb(0, it8716f_flashport);
> /* Wait until the Write-In-Progress bit is cleared.
> * This usually takes 1-10 ms, so wait in 1 ms steps.
> */
> while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
> usleep(1000);
>
> -}
>
> void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
>  {
> if (it8716f_flashport)
> if (it8716f_flashport) {
> it8716f_spi_page_program(block, buf, bios);
> return;
> }
> printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
>
> }
>
> /*
> @@ -452,30 +286,8 @@
>    }
>  }
>
> -/*
> IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
> Program chip using firmware cycle byte programming. (SLOW!)
> */
>
> -int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf)
> +void spi_nbyte_read(int address, uint8_t *bytes, int len)
>  {
> int total_size = 1024 * flash->total_size;
> int i;
> fast_spi = 0;
> spi_disable_blockprotect();
> for (i = 0; i < total_size; i++) {
> spi_write_enable();
> spi_byte_program(i, buf[i]);
> while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
> 	myusec_delay(10);
> }
> /* resume normal ops... */
> outb(0x20, it8716f_flashport);
> return 0;
>
> -}
>
> -void spi_3byte_read(int address, uint8_t *bytes, int len)
> -{
>    const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
>    	(address >> 16) & 0xff,
>    	(address >> 8) & 0xff,
> @@ -486,39 +298,19 @@
>    spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes);
>  }
>
> -/*
> IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
> Need to read this big flash using firmware cycles 3 byte at a time.
> */
>
> int spi_chip_read(struct flashchip *flash, uint8_t *buf)
>  {
> int total_size = 1024 * flash->total_size;
> int i;
> fast_spi = 0;
> if (total_size > 512 * 1024) {
> for (i = 0; i < total_size; i += 3) {
> 	int toread = 3;
> 	if (total_size - i < toread)
> 		toread = total_size - i;
> 	spi_3byte_read(i, buf + i, toread);
> }
> } else {
> memcpy(buf, (const char *)flash->virtual_memory, total_size);
> }
> return 0;
> if (it8716f_flashport)
> return it8716f_spi_chip_read(flash, buf);
> printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
> return 1;
>
> }
>
> -int spi_chip_write(struct flashchip *flash, uint8_t *buf) {
> int total_size = 1024 * flash->total_size;
> int i;
> if (total_size > 512 * 1024) {
> it8716f_over512k_spi_chip_write(flash, buf);
> } else {
> for (i = 0; i < total_size / 256; i++) {
> 	spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
> }
> }
> return 0;
>
> +int spi_chip_write(struct flashchip *flash, uint8_t *buf)
> +{
> if (it8716f_flashport)
> return it8716f_spi_chip_write(flash, buf);
> printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
> return 1;
>
> }
> Index: flashrom-spirestructure/Makefile
>
> --- flashrom-spirestructure/Makefile	(Revision 3302)
> +++ flashrom-spirestructure/Makefile	(Arbeitskopie)
> @@ -24,7 +24,7 @@
>    sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \
>    w49f002u.o 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o \
>    sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \
> flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o
> flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o
>
> all: pciutils dep $(PROGRAM)
> Index: flashrom-spirestructure/it87spi.c
>
> --- /dev/null	2007-09-21 23:50:58.000000000 +0200
> +++ flashrom-spirestructure/it87spi.c	2008-05-13 17:19:55.000000000 +0200
> @@ -0,0 +1,257 @@
> +/*
> This file is part of the flashrom project.
> Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
> Copyright (C) 2008 Ronald Hoogenboom
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; version 2 of the License.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +/*
> Contains the ITE IT87* SPI specific routines
> */
>
> +#include <stdio.h>
> +#include <pci/pci.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include "flash.h"
> +#include "spi.h"
>
> +#define ITE_SUPERIO_PORT1	0x2e
> +#define ITE_SUPERIO_PORT2	0x4e
>
> +uint16_t it8716f_flashport = 0;
> +/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
> +int fast_spi = 1;
>
> +/* Generic Super I/O helper functions */
> +uint8_t regval(uint16_t port, uint8_t reg)
> +{
> outb(reg, port);
> return inb(port + 1);
>
> +}
>
> +void regwrite(uint16_t port, uint8_t reg, uint8_t val)
> +{
> outb(reg, port);
> outb(val, port + 1);
>
> +}
>
> +/* Helper functions for most recent ITE IT87xx Super I/O chips */
> +#define CHIP_ID_BYTE1_REG	0x20
> +#define CHIP_ID_BYTE2_REG	0x21
> +static void enter_conf_mode_ite(uint16_t port)
> +{
> outb(0x87, port);
> outb(0x01, port);
> outb(0x55, port);
> if (port == ITE_SUPERIO_PORT1)
> outb(0x55, port);
> else
> outb(0xaa, port);
>
> +}
>
> +static void exit_conf_mode_ite(uint16_t port)
> +{
> regwrite(port, 0x02, 0x02);
>
> +}
>
> +static uint16_t find_ite_spi_flash_port(uint16_t port)
> +{
> uint8_t tmp = 0;
> uint16_t id, flashport = 0;
> enter_conf_mode_ite(port);
> id = regval(port, CHIP_ID_BYTE1_REG) << 8;
> id |= regval(port, CHIP_ID_BYTE2_REG);
> /* TODO: Handle more IT87xx if they support flash translation */
> if (id == 0x8716) {
> /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
> tmp = regval(port, 0x24) & 0xFE;
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
> printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
> 	0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
> printf("LPC write to serial flash %sabled\n",
> 	(tmp & 1 << 4) ? "en" : "dis");
> printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
> /* LDN 0x7, reg 0x64/0x65 */
> regwrite(port, 0x07, 0x7);
> flashport = regval(port, 0x64) << 8;
> flashport |= regval(port, 0x65);
> }
> exit_conf_mode_ite(port);
> return flashport;
>
> +}
>
> +int it87xx_probe_spi_flash(const char *name)
> +{
> it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
> if (!it8716f_flashport)
> it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
> return (!it8716f_flashport);
>
> +}
>
> +/* The IT8716F only supports commands with length 1,2,4,5 bytes including
> command byte and can not read more than 3 bytes from the device.
> This function expects writearr[0] to be the first byte sent to the device,
> whereas the IT8716F splits commands internally into address and non-address
> commands with the address in inverse wire order. That's why the register
> ordering in case 4 and 5 may seem strange. */
>
> +int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
> +{
> uint8_t busy, writeenc;
> int i;
> do {
> busy = inb(it8716f_flashport) & 0x80;
> } while (busy);
> if (readcnt > 3) {
> printf("%s called with unsupported readcnt %i.\n",
> 	__FUNCTION__, readcnt);
> return 1;
> }
> switch (writecnt) {
> case 1:
> outb(writearr[0], it8716f_flashport + 1);
> writeenc = 0x0;
> break;
> case 2:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 7);
> writeenc = 0x1;
> break;
> case 4:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 4);
> outb(writearr[2], it8716f_flashport + 3);
> outb(writearr[3], it8716f_flashport + 2);
> writeenc = 0x2;
> break;
> case 5:
> outb(writearr[0], it8716f_flashport + 1);
> outb(writearr[1], it8716f_flashport + 4);
> outb(writearr[2], it8716f_flashport + 3);
> outb(writearr[3], it8716f_flashport + 2);
> outb(writearr[4], it8716f_flashport + 7);
> writeenc = 0x3;
> break;
> default:
> printf("%s called with unsupported writecnt %i.\n",
> 	__FUNCTION__, writecnt);
> return 1;
> }
> /* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
> * Note:
> * We can't use writecnt directly, but have to use a strange encoding.
> */ 
> outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
> if (readcnt > 0) {
> do {
> 	busy = inb(it8716f_flashport) & 0x80;
> } while (busy);
> for (i = 0; i < readcnt; i++) {
> 	readarr[i] = inb(it8716f_flashport + 5 + i);
> }
> }
> return 0;
>
> +}
>
> +/* Page size is usually 256 bytes */
> +void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
> int i;
> spi_write_enable();
> outb(0x06 , it8716f_flashport + 1);
> outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
> for (i = 0; i < 256; i++) {
> bios[256 * block + i] = buf[256 * block + i];
> }
> outb(0, it8716f_flashport);
> /* Wait until the Write-In-Progress bit is cleared.
> * This usually takes 1-10 ms, so wait in 1 ms steps.
> */
> while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
> usleep(1000);
>
> +}
>
> +/*
> IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
> Program chip using firmware cycle byte programming. (SLOW!)
> */
>
> +int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf)
> +{
> int total_size = 1024 * flash->total_size;
> int i;
> fast_spi = 0;
> spi_disable_blockprotect();
> for (i = 0; i < total_size; i++) {
> spi_write_enable();
> spi_byte_program(i, buf[i]);
> while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
> 	myusec_delay(10);
> }
> /* resume normal ops... */
> outb(0x20, it8716f_flashport);
> return 0;
>
> +}
>
> +/*
> IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
> Need to read this big flash using firmware cycles 3 byte at a time.
> */
>
> +int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf)
> +{
> int total_size = 1024 * flash->total_size;
> int i;
> fast_spi = 0;
> if (total_size > 512 * 1024) {
> for (i = 0; i < total_size; i += 3) {
> 	int toread = 3;
> 	if (total_size - i < toread)
> 		toread = total_size - i;
> 	spi_nbyte_read(i, buf + i, toread);
> }
> } else {
> memcpy(buf, (const char *)flash->virtual_memory, total_size);
> }
> return 0;
>
> +}
>
> +int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf) {
> int total_size = 1024 * flash->total_size;
> int i;
> if (total_size > 512 * 1024) {
> it8716f_over512k_spi_chip_write(flash, buf);
> } else {
> for (i = 0; i < total_size / 256; i++) {
> 	spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
> }
> }
> return 0;
>
> +}

[Carl-Daniel Hailfinger]

On 14.05.2008 00:22, Peter Stuge wrote:
> On Tue, May 13, 2008 at 05:33:44PM +0200, Carl-Daniel Hailfinger wrote:
> > flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
> > file it87spi.c.
> > No behavioural changes, but greatly improved SPI abstraction.
> >
> > Signed-off-by: Carl-Daniel Hailfinger
>
> I'm good with this! Have not tested though.
>
> Acked-by: Peter Stuge

Thanks, r3305.

Regards,
Carl-Daniel