problem on boot - coreboot

9 May 2003


      this is the full log of minicom
Welcome to minicom 2.00.0
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Compiled on Apr 30 2003, 17:04:09.
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LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 starting...
Copying LinuxBIOS to ram.
LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 booting...
Finding PCI configuration type.
PCI: Using configuration type 1
handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318
handle_superio Pass 0, check #0, s 0000b040 s->super 0000b318
handle_superio: Pass 0, Superio SiS 950
handle_superio  port 0x0, defaultport 0x2e
handle_superio  Using port 0x2e
handle_superio Pass 0, done #0
handle_superio done
Scanning PCI bus...PCI: pci_scan_bus for bus 0
PCI: 00:00.0 [1039/0730]
PCI: 00:00.1 [1039/5513]
PCI: 00:01.0 [1039/0008]
PCI: 00:01.1 [1039/0900]
PCI: 00:01.2 [1039/7001]
PCI: 00:01.3 [1039/7001]
PCI: 00:01.4 [1039/7018]
PCI: 00:01.6 [1039/7013]
PCI: 00:02.0 [1039/0001]
PCI: pci_scan_bus for bus 1
PCI: 01:00.0 [1039/6300]
PCI: pci_scan_bus returning with max=01
PCI: pci_scan_bus returning with max=01
done
totalram: 1016M
Initializing CPU #0
Enabling cache...
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
Setting variable MTRR 1, base:  512MB, range:  256MB, type WB
Setting variable MTRR 2, base:  768MB, range:  128MB, type WB
Setting variable MTRR 3, base:  896MB, range:   64MB, type WB
Setting variable MTRR 4, base:  960MB, range:   32MB, type WB
Setting variable MTRR 5, base:  992MB, range:   16MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
call intel_enable_fixed_mtrr()
call intel_enable_var_mtrr()
Leave setup_mtrrs
done.
Max cpuid index    : 1
Vendor ID          : AuthenticAMD
Processor Type     : 0x00
Processor Family   : 0x06
Processor Model    : 0x08
Processor Mask     : 0x00
Processor Stepping : 0x00
Feature flags      : 0x0183f9ff
MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled
Disabling local apic...done.
CPU #0 Initialized
Allocating PCI resources...
ASSIGN RESOURCES, bus 0
PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem
PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io
PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io
PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io
PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io
PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io
PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io
PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem
PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem
PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem
PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io
PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem
PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io
PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io
PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ??????io
PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ??????prefmem
PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ??????mem
ASSIGN RESOURCES, bus 1
PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem
PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem
PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io
Allocating VGA resource
done.
Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07
PCI: 00:00.1 cmd <- 01
PCI: 00:01.0 cmd <- 0c
PCI: 00:01.1 cmd <- 03
PCI: 00:01.2 cmd <- 02
PCI: 00:01.3 cmd <- 02
PCI: 00:01.4 cmd <- 03
PCI: 00:01.6 cmd <- 01
PCI: 00:02.0 cmd <- 27
PCI: 01:00.0 cmd <- 03
done.
Initializing PCI devices...
PCI devices initialized
Enabled in SIS 503 regs 0x40 and 0x45
handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318
handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318
handle_superio: Pass 1, Superio SiS 950
handle_superio  port 0x2e, defaultport 0x2e
handle_superio  Using port 0x2e
handle_superio Pass 1, done #0
handle_superio done
PCCHIPS M810LMR (and similar)...Entering the initregs process
Southbridge fixup done for SIS 503
handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318
handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318
handle_superio: Pass 2, Superio SiS 950
handle_superio  port 0x2e, defaultport 0x2e
handle_superio  Using port 0x2e
  Call finishup
handle_superio Pass 2, done #0
handle_superio done
Copying IRQ routing tables to 0xf0000...done.
Wrote linuxbios table at: 00000500 - 0000066c  checksum ba14
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
37:init_bytes() - zkernel_start:0xfffc0000  zkernel_mask:0x0000ffff
Found ELF candiate at offset 0
New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789
(cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789
Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 
0x0000000000008789
Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417
Jumping to boot code
ROM segment 0x0000 length 0x0000 reloc 0x0000
Etherboot 5.0.6 (GPL) ELF for [SIS900]
Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784463
N
I am now initializing the ide system
init_drive sectors_per_track = [0], num_heads = [0],num_cylinders=[0], 
num_sectors = [0]
CHS mode...
Boot: (hd0,0)/kernel
this is the output of the serial boot n boot.
Tnx Serafino