v2 epia-m progress - coreboot

21 Nov 2003


      I did a quick hack to enable the DDR memory just like v1's epia-m hack.
The northbridge.c just has a single function sizeram() which I implemented
to just return as if there is 64M of memory. I commented out the
attempts to init the smbus + sdram, and let everything proceed. It got
to the etherboot payload, requested a bootfile, loaded it, launched linux,
and initialized linux quite well, then crapped out trying to do network
activity. It is obviously an interrupt problem, packets are coming out of
the box but it can't receive them.
This is very encouraging after about 3 hours or so. I haven't really done
any initialization of either the north or south bridge, just the hack to
initialize the DDR memory. I converted the asm code to 'C' but it is
still hardcoded as opposed to reading the SPD contents.
This was actually a surprise, I was expecting it to fail further along in
linuxbios and suddenly all these linux messages were coming out.
-Dave