[commit] r5902 - in trunk/src: cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86
Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902
Log: Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code.
For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Peter Stuge peter@stuge.se
Added: trunk/src/include/cpu/x86/car.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h>
@@ -45,8 +46,7 @@ * xmm3: Backup EBX */
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
/* * For normal part %ebx already contain cpu_init_detected @@ -56,10 +56,7 @@ cache_as_ram_setup: post_code(0xa0)
- /* Enable SSE. */ - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 + enable_sse()
/* Figure out the CPU family. */ cvtsi2sd %ebx, %xmm3 @@ -299,10 +296,7 @@
post_code(0xa1)
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
jmp_if_k8(fam10_end_part1)
@@ -384,13 +378,9 @@
post_code(0xa5)
- /* Disable SSE. */ - movl %cr4, %eax - andl $~(3 << 9), %eax - movl %eax, %cr4 + disable_sse()
- /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result()
/* We need to set EBP? No need. */ movl %esp, %ebp
Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -21,6 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> @@ -28,8 +29,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize)
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
CacheAsRam: /* Check whether the processor has HT capability. */ @@ -231,10 +231,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
/* Read the range with lodsl. */ movl $CacheBase, %esi @@ -295,8 +292,7 @@ movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result()
/* We need to set EBP? No need. */ movl %esp, %ebp @@ -305,10 +301,7 @@
/* We don't need CAR from now on. */
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
/* Clear sth. */ movl $MTRRfix4K_C8000_MSR, %ecx @@ -330,10 +323,7 @@ movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache();
/* Clear boot_complete flag. */ xorl %ebp, %ebp
Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ xorl %edx, %edx wrmsr
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
- /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
/* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp
- /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax
@@ -144,18 +132,11 @@
post_code(0x30)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x31)
- /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr()
post_code(0x31)
@@ -175,17 +156,11 @@
post_code(0x33)
- /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x36)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x38)
@@ -202,17 +177,11 @@ post_code(0x39)
/* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x3a)
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
post_code(0x3b)
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ movl $0x0000000f, %edx wrmsr
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
- /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
/* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp
- /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax
@@ -144,18 +132,11 @@
post_code(0x30)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x31)
- /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr()
post_code(0x31)
@@ -175,17 +156,11 @@
post_code(0x33)
- /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x36)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x38)
@@ -202,17 +177,11 @@ post_code(0x39)
/* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x3a)
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
post_code(0x3b)
Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
cache_as_ram: post_code(0x20) @@ -73,19 +73,12 @@ movl $0x0000000f, %edx wrmsr
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
- /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache()
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -100,9 +93,7 @@ rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -123,10 +114,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
/* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -137,8 +125,8 @@ #endif movl %eax, %esp
- /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax
@@ -151,18 +139,11 @@
post_code(0x30)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x31)
- /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr()
post_code(0x31)
@@ -182,17 +163,11 @@
post_code(0x33)
- /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x36)
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
post_code(0x38)
@@ -209,17 +184,11 @@ post_code(0x39)
/* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache()
post_code(0x3a)
- /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr()
post_code(0x3b)
Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -25,21 +25,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE
- /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result()
CacheAsRam:
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() invd
/* Set the default memory type and enable fixed and variable MTRRs. */ @@ -116,10 +113,7 @@ movl $(MTRRdefTypeEn), %eax wrmsr
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache()
/* Read the range with lodsl. */ cld @@ -175,8 +169,7 @@ jne stackerr #endif
- /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result()
/* We need to set EBP? No need. */ movl %esp, %ebp @@ -191,10 +184,7 @@
/* We don't need CAR from now on. */
- /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache()
/* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ @@ -253,10 +243,7 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr
- /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() invd
/* Clear boot_complete flag. */
Added: trunk/src/include/cpu/x86/car.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/car.h Fri Oct 1 23:46:04 2010 (r5902) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/mtrr.h> + +/* Save the BIST result. */ +#define save_bist_result() \ + movl %eax, %ebp + +/* Restore the BIST result. */ +#define restore_bist_result() \ + movl %ebp, %eax + +/* Enable cache. */ +#define enable_cache() \ + movl %cr0, %eax; \ + andl $(~((1 << 30) | (1 << 29))), %eax; \ + movl %eax, %cr0 + +/* Disable cache. */ +#define disable_cache() \ + movl %cr0, %eax; \ + orl $(1 << 30), %eax; \ + movl %eax, %cr0 + +/* Enable MTRR. */ +#define enable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + orl $(1 << 11), %eax; \ + wrmsr + +/* Disable MTRR. */ +#define disable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + andl $(~(1 << 11)), %eax; \ + wrmsr + +/* Enable L2 cache. */ +#define enable_l2_cache() \ + movl $0x11e, %ecx; \ + rdmsr; \ + orl $(1 << 8), %eax; \ + wrmsr + +/* Enable SSE. */ +#define enable_sse() \ + movl %cr4, %eax; \ + orl $(3 << 9), %eax; \ + movl %eax, %cr4 + +/* Disable SSE. */ +#define disable_sse() \ + movl %cr4, %eax; \ + andl $~(3 << 9), %eax; \ + movl %eax, %cr4 +
On Fri, Oct 01, 2010 at 11:46:05PM +0200, repository service wrote:
Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902
Log: Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code.
For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Peter Stuge peter@stuge.se
I'd like to express my disapointment that this patch went in. Today I updated my repo and went to find out why my epia-cn reverted (yet again) to doing lzma uncompression without caching. I had to wade through the effects of this patch. This patch is a regression - it makes the code harder to understand.
-Kevin
* Kevin O'Connor kevin@koconnor.net [110116 20:04]:
On Fri, Oct 01, 2010 at 11:46:05PM +0200, repository service wrote:
Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902
Log: Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code.
For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Peter Stuge peter@stuge.se
I'd like to express my disapointment that this patch went in. Today I updated my repo and went to find out why my epia-cn reverted (yet again) to doing lzma uncompression without caching. I had to wade through the effects of this patch. This patch is a regression - it makes the code harder to understand.
-Kevin
I agree. And I would like to back it out. Will do so if I get 2 acks.
Signed-off-by: Stefan Reinauer stepan@coreboot.org
Hi,
If possible I would like to see it back too.
Acked-by: Rudolf Marek r.marek@assembler.cz
Thanks, Rudolf
On Sun, Jan 16, 2011 at 10:38:54PM +0100, Stefan Reinauer wrote:
- Kevin O'Connor kevin@koconnor.net [110116 20:04]:
On Fri, Oct 01, 2010 at 11:46:05PM +0200, repository service wrote:
Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902
Log: Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code.
For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Peter Stuge peter@stuge.se
I'd like to express my disapointment that this patch went in. Today I updated my repo and went to find out why my epia-cn reverted (yet again) to doing lzma uncompression without caching. I had to wade through the effects of this patch. This patch is a regression - it makes the code harder to understand.
-Kevin
I agree. And I would like to back it out. Will do so if I get 2 acks.
Signed-off-by: Stefan Reinauer stepan@coreboot.org
Acked-by: Kevin O'Connor kevin@koconnor.net
-Kevin
I just noticed AMD has a family 14h BKDG on their website:
http://developer.amd.com/documentation/guides/pages/default.aspx
Thanks, Scott
-
Kevin O'Connor -
repository service -
Rudolf Marek -
Scott Duplichan -
Stefan Reinauer