Hello Zvika: 1.- Usually it is not necessary to change the CBFS size unless the compiler complain of lack of space. 2.- You should not worry about this setting to make your system to work. 3.- You should not use FSP_PACKAGE_DEFAULT if your plan is to use SIO because it will enable SOC internal COM1, instead (if your plan is to use FSP) enable FSP and add a VGA bios bin manually.... (The use of FSP is optional but I never tried without FSP). 4.- You need to add them yourself, there are examples to follow in this mail list. Good luck! J.Trujillo
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On June 18, 2018 6:24 AM, Zvi Vered veredz72@gmail.com wrote:
Hello, I inspected the "Bayley Baay FSP-based CRB" sample in coreboot. after make distclean I chose: Mainboard vendor: Intel Mainboard model: Bayley Bay FSP-based CRB
- The size of CBFS is: 0x200000. Is it a fix size or should I change it according to my board (which is also bay trail) ?
- According to "dmidecode" I ran on my target, "Address: 0xE0000"
Should I set this address in coreboot configuration ? How ?
- In this board default configuration, "Configure defaults for the Intel FSP package" is not selected. Is it possible that this board does not use Intel FSP at all ?
Under "Generic Drivers", "Use Intel firmware Support Package' is also not selected.
- Under "chipset", there is no option to set "Super I/O". Can you please tell why ?
- I noticed that the minimum ROM size is 2MB. If I set 4MB, the size of coreboot.rom is also 4MB.
Thank you in advance, Zvika
-
Jose Trujillo