link representation in v3 dts - coreboot

7 Sep 2008

      Since link representation is a difficult topic to understand and present
cleanly, I tried to use the v2 S2892 Config.lb into a v3 dts. Attached
are a shortened version of the v2 Config.lb and the mostly matching v3 dts.
Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/

/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

/{
    mainboard_vendor = "Tyan";
    mainboard_name = "S2892";
    cpus { };
    apic@0 {
    };
    domain@0 {
    	pci@18,0 { 
    		children_as_links;
    		link@0 {
    			pci@0,0 { /* HT */
    				/config/("southbridge/nvidia/ck804/dts");
    			};
    			pci@1,0 { /* LPC */
    			};
    			pci@1,1 { /* SMBUS */
    				children_as_links;
    				/*Fill in here*/
    			};
    			pci@2,0 { /* USB 1.1 */
    			};
    			pci@2,1 { /* USB 2.0 */
    			};
    			pci@4,0 { /* ACI */
    			};
    			pci@4,1 { /* MCI */
    			};
    			pci@6,0 { /* IDE */
    			};
    			pci@7,0 { /* SATA 1 */
    			};
    			pci@8,0 { /* SATA 0 */
    			};
    			pci@9,0 { /* PCI */
    				bus@0 { /* Fill in here */
    				};
    			};
    			pci@a,0 { /* NIC */
    			};
    			pci@b,0 { /* PCIe 3 */
    			};
    			pci@c,0 { /* PCIe 2 */
    			};
    			pci@d,0 { /* PCIe 1 */
    			};
    			pci@e,0 { /* PCIe 0 */
    			};
    		};
    		link@1 {
    		};
    		link@2 {
    			pci@0,0 { /* HT */
    				/config/("southbridge/amd/amd8131/dts");
    			};
    			pci@0,1 {
    			};
    			pci@1,0 {
    				bus@0 {
    					pci@9,0 { /* Broadcom 5704 */
    					};
    					pci@9,1 {
    					};
    				};
    			};
    			pci@1,1 {
    			};
    		};
    	};
    	pci@18,1 {
    	};
    	pci@18,2 {
    	};
    	pci@18,3 {
    	};
    	ioport@2e {
    		/config/("superio/winbond/w83627hf/dts");
    		com1enable = "1";
    	};
    };
};

# sample config for tyan/s2892
chip northbridge/amd/amdk8/root_complex
    device apic_cluster 0 on
    	chip cpu/amd/socket_940
    		device apic 0 on end
    	end
    end
    device pci_domain 0 on
    	chip northbridge/amd/amdk8 #mc0
    		device pci 18.0 on #  northbridge
    			#  devices on link 0, link 0 == LDT 0
    			chip southbridge/nvidia/ck804
    				device pci 0.0 on end   # HT
    				device pci 1.0 on # LPC
    				device pci 1.1 on # SM 0
    				device pci 1.1 on # SM 1
    				device pci 2.0 on end # USB 1.1
    				device pci 2.1 on end # USB 2
    				device pci 4.0 off end # ACI
    				device pci 4.1 off end # MCI
    				device pci 6.0 on end # IDE
    				device pci 7.0 on end # SATA 1
    				device pci 8.0 on end # SATA 0
    				device pci 9.0 on  # PCI
    					chip drivers/pci/onboard
    						device pci 6.0 on end
    					end
    					chip drivers/pci/onboard
    						device pci 8.0 on end
    					end
    				end
    				device pci a.0 off end # NIC
    				device pci b.0 off end # PCI E 3
    				device pci c.0 off end # PCI E 2
    				device pci d.0 on end # PCI E 1
    				device pci e.0 on end # PCI E 0
    			end
    		end #  device pci 18.0
    		device pci 18.0 on end # Link 1
    		device pci 18.0 on
    			#  devices on link 2, link 2 == LDT 2
    			chip southbridge/amd/amd8131
    				# the on/off keyword is mandatory
    				device pci 0.0 on end
    				device pci 0.1 on end
    				device pci 1.0 on
    					chip drivers/pci/onboard
    						device pci 9.0 on end # broadcom 5704
    						device pci 9.1 on end
    					end
    				end
    				device pci 1.1 on end
    			end
    		end # device pci 18.0
    		device pci 18.1 on end
    		device pci 18.2 on end
    		device pci 18.3 on end
    	end #mc0
    end # pci_domain
end # root_complex