Author: rminnich Date: 2008-08-14 19:00:11 +0200 (Thu, 14 Aug 2008) New Revision: 765
Modified: coreboot-v3/northbridge/amd/k8/raminit.c Log: Continue cleaning up pci calls in stage1. Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-14 16:31:24 UTC (rev 764) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-14 17:00:11 UTC (rev 765) @@ -39,9 +39,9 @@ #include <amd/k8/k8.h> #include <amd/k8/sysconf.h> #include <device/pci.h> +#include <pci_ops.h> #include <mc146818rtc.h> #include <lib.h> -#include "stage1.h"
#ifndef QRANK_DIMM_SUPPORT #define QRANK_DIMM_SUPPORT 0 @@ -56,7 +56,7 @@
static int controller_present(const struct mem_controller *ctrl) { - return pci_read_config32(ctrl->f0, 0) == 0x11001022; + return pci_conf1_read_config32(ctrl->f0, 0) == 0x11001022; }
void sdram_set_registers(const struct mem_controller *ctrl) @@ -545,8 +545,8 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) { u32 dcl, nbcap, opt = 1; - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; @@ -554,14 +554,14 @@ if (get_option(&opt, "ECC_memory") || opt) { dcl &= ~DCL_DimmEccEn; } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); }
static int is_dual_channel(const struct mem_controller *ctrl) { u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_128BitEn; }
@@ -573,7 +573,7 @@ */ #warning "FIXME: Implement a better test for Opterons" u32 nbcap; - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); }
@@ -584,7 +584,7 @@ * This function must be called after spd_handle_unbuffered_dimms. */ u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBufDimm); }
@@ -716,25 +716,25 @@ base1 &= ~0x001ffffe;
/* Set the appropriate DIMM base address register */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); } #endif
/* Enable the memory clocks for this DIMM */ if (base0) { - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_MEMCLK_EN0 << index; #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } #endif - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } }
@@ -750,7 +750,7 @@ u32 map; u32 dch;
- map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + map = pci_conf1_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { @@ -779,7 +779,7 @@ } }
- pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); + pci_conf1_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); }
@@ -826,8 +826,8 @@ limit_reg = 0x44 + index; base_reg = 0x40 + index; for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) { - pci_write_config32(device, limit_reg, limit); - pci_write_config32(device, base_reg, base); + pci_conf1_write_config32(device, limit_reg, limit); + pci_conf1_write_config32(device, base_reg, base); } }
@@ -912,7 +912,7 @@ unsigned cs_mode; u32 value; - value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) { @@ -928,7 +928,7 @@ return 0; }
- value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + value = pci_conf1_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); cs_mode =( value >> ((index>>1)*4)) & 0xf; if(cs_mode == 0 ) continue; if(common_cs_mode == 0) { @@ -981,13 +981,13 @@ for(index = 0; index < 8; index++) { u32 value;
- value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) { continue; } - pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase); - pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase); + pci_conf1_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask); csbase += csbase_inc; } @@ -1012,7 +1012,7 @@ candidate = 0; for(index = 0; index < 8; index++) { u32 value; - value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */ if (!(value & 1)) { @@ -1054,9 +1054,9 @@ csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase); /* Write the new mask register */ - pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask); + pci_conf1_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask); } /* Return the memory size in K */ @@ -1073,10 +1073,10 @@ u32 limit, base; unsigned index; index = node_id << 3; - base = pci_read_config32(ctrl->f1, 0x40 + index); + base = pci_conf1_read_config32(ctrl->f1, 0x40 + index); /* Only look at the limit if the base is enabled */ if ((base & 3) == 3) { - limit = pci_read_config32(ctrl->f1, 0x44 + index); + limit = pci_conf1_read_config32(ctrl->f1, 0x44 + index); end_k = ((limit + 0x00010000) & 0xffff0000) >> 2; } } @@ -1107,8 +1107,8 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) { printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); dimm_mask &= ~(1 << index); return dimm_mask; } @@ -1144,7 +1144,7 @@ die("Mixed buffered and registered dimms not supported"); }
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_UnBufDimm; if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { @@ -1160,7 +1160,7 @@ dcl |= DCL_UnBufDimm; } } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); if (is_registered(ctrl)) { printk(BIOS_DEBUG, "Registered\n"); } else { @@ -1228,7 +1228,7 @@ goto single_channel; } /* If the cpu is not capable of doing dual channels don't do dual channels */ - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; } @@ -1260,10 +1260,10 @@ } printk(BIOS_SPEW, "Enabling dual channel memory\n"); u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_32ByteEn; dcl |= DCL_128BitEn; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return dimm_mask; single_channel: dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS)); @@ -1384,7 +1384,7 @@ [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ };
- value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + value = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
@@ -1535,7 +1535,7 @@ result.param = get_mem_param(min_cycle_time);
/* Update DRAM Config High with our selected memory speed */ - value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed @@ -1549,14 +1549,14 @@ #endif
value |= result.param->dch_memclk; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; /* Update DRAM Timing Low with our selected cas latency */ - value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + value = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; return result; @@ -1585,14 +1585,14 @@ return 0; }
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT); dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
@@ -1613,14 +1613,14 @@ if (clocks > DTL_TRFC_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT); dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
@@ -1639,14 +1639,14 @@ if (clocks > DTL_TRCD_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT); dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
@@ -1664,14 +1664,14 @@ if (clocks > DTL_TRRD_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT); dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
@@ -1689,14 +1689,14 @@ if (clocks > DTL_TRAS_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
@@ -1714,34 +1714,34 @@ if (clocks > DTL_TRP_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT); dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; }
static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dtl; - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT); dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT; - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); }
static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dth; - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (param->dch_tref4k << DTH_TREF_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); }
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) @@ -1758,7 +1758,7 @@ tref = param->dch_tref4k; }
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK; if ((value == 12) && (old_tref == param->dch_tref4k)) { tref = param->dch_tref4k; @@ -1767,7 +1767,7 @@ } dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (tref << DTH_TREF_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return 1; }
@@ -1798,12 +1798,12 @@ dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~dimm; if (value == 4) { dcl |= dimm; } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return 1; }
@@ -1816,9 +1816,9 @@ return -1; } if (value != 2) { - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } return 1; } @@ -1830,7 +1830,7 @@ dimms = 0; for(index = 0; index < 8; index += 2) { u32 csbase; - csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); + csbase = pci_conf1_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); if (csbase & 1) { dimms += 1; } @@ -1842,10 +1842,10 @@ { u32 dth;
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT); dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); }
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1856,7 +1856,7 @@ int lat = 0, mtype;
clocks = 0; - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
if (is_opteron(ctrl)) { @@ -1886,10 +1886,10 @@ die("Unknown Trwt\n"); } - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT); dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return; }
@@ -1903,10 +1903,10 @@ } else { clocks = 1; } - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT); dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); }
@@ -1937,7 +1937,7 @@ die("Unknown rdpreamble for this nr of slots"); }
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT); rdpreamble = param->rdpreamble[i];
@@ -1946,7 +1946,7 @@ }
dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); }
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1957,7 +1957,7 @@
dimms = count_dimms(ctrl);
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT); async_lat = 0; if (is_registered(ctrl)) { @@ -1984,18 +1984,18 @@ } } dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT); - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); }
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dch; /* AMD says to Hardcode this */ - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT); dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT; dch |= DCH_DYN_IDLE_CTR_EN; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); }
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask) @@ -2103,22 +2103,22 @@ carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) { - base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); - pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); } } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (i << 3)); for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); } dev = ctrl[i].f1; - base = pci_read_config32(dev, 0x40 + (i << 3)); + base = pci_conf1_read_config32(dev, 0x40 + (i << 3)); basek = (base & 0xffff0000) >> 2; if(basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow @@ -2126,7 +2126,7 @@ base &= 0x0000ffff; base |= (4*1024*1024)<<2; for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + pci_conf1_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); } } else { @@ -2136,7 +2136,7 @@ (((basek + carry_over) >> 6) & 0x0000ff00) + /* enable */ 1; - pci_write_config32(dev, 0xf0, hoist); + pci_conf1_write_config32(dev, 0xf0, hoist); }
return carry_over; @@ -2160,7 +2160,7 @@ for(i=0; i<controllers; i++) { u32 base; unsigned base_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } @@ -2180,11 +2180,11 @@ for(i=0; i<controllers; i++) { u32 base, limit; unsigned base_k, limit_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (i << 3)); base_k = (base & 0xffff0000) >> 2; limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; if ((base_k <= hole_startk) && (limit_k > hole_startk)) { @@ -2215,17 +2215,17 @@ u32 dch; if (!controller_present(ctrl + i)) continue; - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) { dch |= DCH_MEMCLK_VALID; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); } else { /* Disable dram receivers */ u32 dcl; - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); dcl |= DCL_DisInRcvrs; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); } }
@@ -2239,31 +2239,31 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (!(dch & DCH_MEMCLK_VALID)) { continue; }
/* Toggle DisDqsHys to get it working */ - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { u32 mnc; printk(BIOS_SPEW, "ECC enabled\n"); - mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); + mnc = pci_conf1_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_128BitEn) { mnc |= MNC_CHIPKILL_EN; } - pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); + pci_conf1_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); } dcl |= DCL_DisDqsHys; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); dcl &= ~DCL_DisDqsHys; dcl &= ~DCL_DLL_Disable; dcl &= ~DCL_D_DRV; dcl &= ~DCL_QFC_EN; dcl |= DCL_DramInit; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
} for(i = 0; i < controllers; i++) { @@ -2271,7 +2271,7 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (!(dch & DCH_MEMCLK_VALID)) { continue; } @@ -2280,7 +2280,7 @@
int loops = 0; do { - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops += 1; if ((loops & 1023) == 0) { printk(BIOS_DEBUG, "."); @@ -2294,9 +2294,9 @@ if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ dcl &= ~(DCL_MemClrStatus | DCL_DramEnable); - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); do { - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) ); }
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