[commit] r6374 - in trunk/src: mainboard/getac/p470 mainboard/ibase/mb899 mainboard/intel/d945gclf mainboard/kontron/986lcd-m mainboard/lenovo/x60 mainboard/roda/rk886ex northbridge/intel/i945

[repository service]

Author: svens
Date: Mon Feb 21 10:39:17 2011
New Revision: 6374
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6374

Log:
[i945] Add SPD adress mapping

The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.

For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.

This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.

Signed-off-by: Sven Schnelle 
Acked-by: Patrick Georgi

Modified:
   trunk/src/mainboard/getac/p470/romstage.c
   trunk/src/mainboard/ibase/mb899/romstage.c
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/lenovo/x60/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/northbridge/intel/i945/raminit.c
   trunk/src/northbridge/intel/i945/raminit.h

Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/getac/p470/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -332,7 +332,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/ibase/mb899/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -283,7 +283,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -243,7 +243,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -382,7 +382,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/mainboard/lenovo/x60/romstage.c
==============================================================================
--- trunk/src/mainboard/lenovo/x60/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/lenovo/x60/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -294,6 +294,7 @@
 {
    u32 reg32;
    int boot_mode = 0;
+	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };

if (bist == 0)
    	enable_lapic();
@@ -357,7 +358,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, spd_addrmap);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -320,7 +320,7 @@
    dump_spd_registers();
 #endif

-	sdram_initialize(boot_mode);
+	sdram_initialize(boot_mode, NULL);

/* Perform some initialization that must run before stage2 */
    early_ich7_init();

Modified: trunk/src/northbridge/intel/i945/raminit.c
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.c	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/northbridge/intel/i945/raminit.c	Mon Feb 21 10:39:17 2011	(r6374)
@@ -54,6 +54,15 @@
 #define RAM_EMRS_2			(0x1 << 21)
 #define RAM_EMRS_3			(0x2 << 21)

+static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
+{
+	if (sysinfo->spd_addresses)
+		return sysinfo->spd_addresses[device];
+	else
+		return DIMM0 + device;
+
+}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
    return smbus_read_byte(device, address);
@@ -367,7 +376,8 @@
     */

for (i=0; i<(2 * DIMM_SOCKETS); i++) {
-		u8 reg8, device = DIMM0 + i;
+		int device = get_dimm_spd_address(sysinfo, i);
+		u8 reg8;

/* Initialize the socket information with a sane value */
    	sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -458,7 +468,7 @@
    		continue;

/* Is the current DIMM a stacked DIMM? */
-		if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+		if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4))
    		sysinfo->package = 1;
    }
 }
@@ -475,7 +485,8 @@

for (i=0; i<2*DIMM_SOCKETS; i++) {
    	if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
-			cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+			cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i),
+						  SPD_ACCEPTABLE_CAS_LATENCIES);
    }

if(!cas_mask) {
@@ -529,6 +540,7 @@

PRINTK_DEBUG("Probing Speed %d\n", j);
    	for (i=0; i<2*DIMM_SOCKETS; i++) {
+			int device = get_dimm_spd_address(sysinfo, i);
    		int current_cas_mask;

PRINTK_DEBUG("  DIMM: %d\n", i);
@@ -536,7 +548,7 @@
    			continue;
    		}

-			current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+			current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES);

while (current_cas_mask) {
    			int highest_supported_cas = 0, current_cas = 0;
@@ -562,11 +574,11 @@

idx = highest_supported_cas - current_cas;
    			PRINTK_DEBUG("idx=%d, ", idx);
-				PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
-				PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
+				PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx]));
+				PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1]));

-				if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
-						spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+				if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+						spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
    				PRINTK_DEBUG(":    OK\n");
    				break;
    			}
@@ -630,7 +642,7 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+		reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
    	if (!reg8) {
    		die("Invalid tRAS value.\n");
    	}
@@ -670,7 +682,7 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
+		reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME);
    	if (!reg8) {
    		die("Invalid tRP value.\n");
    	}
@@ -711,7 +723,7 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
+		reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY);
    	if (!reg8) {
    		die("Invalid tRCD value.\n");
    	}
@@ -751,7 +763,7 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
+		reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME);
    	if (!reg8) {
    		die("Invalid tWR value.\n");
    	}
@@ -832,7 +844,8 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
+		refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i),
+					SPD_REFRESH) & ~(1 << 7);

/* 15.6us */
    	if (!refresh)
@@ -860,7 +873,8 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+		if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i),
+				    SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
    		die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
    }
 }
@@ -1392,12 +1406,13 @@
    unsigned long side2;
 };

-static struct dimm_size sdram_get_dimm_size(u16 device)
+static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno)
 {
    /* Calculate the log base 2 size of a DIMM in bits */
    struct dimm_size sz;
-	int value, low, rows, columns;
+	int value, low, rows, columns, device;

+	device = get_dimm_spd_address(sysinfo, dimmno);
    sz.side1 = 0;
    sz.side2 = 0;

@@ -1480,9 +1495,10 @@
    	if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
    		continue;

-		sz = sdram_get_dimm_size(DIMM0 + i);
+		sz = sdram_get_dimm_size(sysinfo, i);

-		sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM);	/* banks */
+		sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i),
+						  SPD_NUM_BANKS_PER_SDRAM);	/* banks */

if (sz.side1 < 30)
    		die("DDR-II rank size smaller than 128MB is not supported.\n");
@@ -1574,7 +1590,7 @@
    		continue;
    	}

-		device = DIMM0 + i;
+		device = get_dimm_spd_address(sysinfo, i);

value = spd_read_byte(device, SPD_NUM_ROWS);	/* rows */
    	columnsrows = (value & 0x0f);
@@ -3039,7 +3055,7 @@
 /**
  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
  */
-void sdram_initialize(int boot_path)
+void sdram_initialize(int boot_path, const u8 *spd_addresses)
 {
    struct sys_info sysinfo;
    u8 reg8, cas_mask;
@@ -3049,6 +3065,7 @@
    memset(&sysinfo, 0, sizeof(sysinfo));

sysinfo.boot_path = boot_path;
+	sysinfo.spd_addresses = spd_addresses;

/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
    sdram_get_dram_configuration(&sysinfo);

Modified: trunk/src/northbridge/intel/i945/raminit.h
==============================================================================
--- trunk/src/northbridge/intel/i945/raminit.h	Sat Feb 19 15:51:31 2011	(r6373)
+++ trunk/src/northbridge/intel/i945/raminit.h	Mon Feb 21 10:39:17 2011	(r6374)
@@ -63,11 +63,12 @@
    u8 banks[2 * DIMM_SOCKETS];

u8 banksize[2 * 2 * DIMM_SOCKETS];
+	const u8 *spd_addresses;

} __attribute__ ((packed));

void receive_enable_adjust(struct sys_info *sysinfo);
-void sdram_initialize(int boot_path);
+void sdram_initialize(int boot_path, const u8 *sdram_addresses);
 unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
 void udelay(u32 us);