A week ago I wrote here about my problems trying to port coreboot to my board. Unfortunately I am still no closer to booting.
In the meantime I flashed my new chip with my OEM firmware backup. It boots; then I flashed my patched IFD (for chip ID and flash unlock) and it still boots. So it's not chip compatibility or corrupted descriptor.
The only sign of life I got is the bootblock banner left in the SPI console. My PCI POST card is showing nothing, but knowing that it sits on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not knowing if it needs software init to work, I am now trying to pull POST codes off the LPC bus over the TPM header, using an Arduino Due. Do I have to add some early init to have port 80 accesses sent to LPC bus for this to work?
Thanks for your help Keith
Hi Keith,
On Fri, Feb 28, 2020 at 7:18 AM Keith Hui buurin@gmail.com wrote:
A week ago I wrote here about my problems trying to port coreboot to my board. Unfortunately I am still no closer to booting.
In the meantime I flashed my new chip with my OEM firmware backup. It boots; then I flashed my patched IFD (for chip ID and flash unlock) and it still boots. So it's not chip compatibility or corrupted descriptor.
The only sign of life I got is the bootblock banner left in the SPI console. My PCI POST card is showing nothing, but knowing that it sits on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not knowing if it needs software init to work, I am now trying to pull POST codes off the LPC bus over the TPM header, using an Arduino Due. Do I have to add some early init to have port 80 accesses sent to LPC bus for this to work?
You have to tell coreboot where to route LPC post codes to. It defaults to "None", but you can choose PCI or LPC. I have never tried to print post codes with coreboot, though. I would try using the serial port though, as it is more practical for debugging than post codes.
Thanks for your help Keith _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards,
Angel Pons
Hi Keith,
PCI-to-PCI bridge need to be configured before you can use PCI POST card.
Default post code are send out to port 80h. Depending on the chipset (and your needs) you need to enable the port80 to the right channel PCI/LPC.
Best regards, Frans Hendriks Eltan B.V.
-----Original Message----- From: Angel Pons [mailto:th3fanbus@gmail.com] Sent: vrijdag 28 februari 2020 10:30 To: Keith Hui buurin@gmail.com Cc: coreboot coreboot@coreboot.org Subject: [coreboot] Re: Still need assistance porting to ASUS P8Z77-M
Hi Keith,
On Fri, Feb 28, 2020 at 7:18 AM Keith Hui buurin@gmail.com wrote:
A week ago I wrote here about my problems trying to port coreboot to my board. Unfortunately I am still no closer to booting.
In the meantime I flashed my new chip with my OEM firmware backup. It boots; then I flashed my patched IFD (for chip ID and flash unlock) and it still boots. So it's not chip compatibility or corrupted descriptor.
The only sign of life I got is the bootblock banner left in the SPI console. My PCI POST card is showing nothing, but knowing that it sits on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not knowing if it needs software init to work, I am now trying to pull POST codes off the LPC bus over the TPM header, using an Arduino Due. Do I have to add some early init to have port 80 accesses sent to LPC bus for this to work?
You have to tell coreboot where to route LPC post codes to. It defaults to "None", but you can choose PCI or LPC. I have never tried to print post codes with coreboot, though. I would try using the serial port though, as it is more practical for debugging than post codes.
Thanks for your help Keith _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards,
Angel Pons _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Frans,
Thanks for confirming.
Hi Angel,
I was unable to get any serial output, even with early serial configured.
Z77 power on defaults will see port 80 decoded by LPC according to their datasheet, and I found Asus actually included with some boards a POST card that plugs into the TPM header, so I'm on the right track. Now to see if I can implement the LPC protocol correctly on an Arduino Due, chosen for its 84MHz clock and 3.3v operation.
I looked at the source and only see the CONFIG_POST_DEVICE_* options used by sb/amd/*/hudson, not by any Intel platform code.
I then looked at the datasheet and the lspci dump with OEM BIOS. I would need to do something to device 0x1e.0 (disabled!) and 0x1c.6 (PCIe root port 6) and I would need new code that connects to CONFIG_POST_DEVICE_*.
I will be back with more questions, so bear with me.
Thanks Keith
On Fri, Feb 28, 2020 at 4:54 AM Frans Hendriks fhendriks@eltan.com wrote:
Hi Keith,
PCI-to-PCI bridge need to be configured before you can use PCI POST card.
Default post code are send out to port 80h. Depending on the chipset (and your needs) you need to enable the port80 to the right channel PCI/LPC.
Best regards, Frans Hendriks Eltan B.V.
-----Original Message----- From: Angel Pons [mailto:th3fanbus@gmail.com] Sent: vrijdag 28 februari 2020 10:30 To: Keith Hui buurin@gmail.com Cc: coreboot coreboot@coreboot.org Subject: [coreboot] Re: Still need assistance porting to ASUS P8Z77-M
Hi Keith,
On Fri, Feb 28, 2020 at 7:18 AM Keith Hui buurin@gmail.com wrote:
A week ago I wrote here about my problems trying to port coreboot to my board. Unfortunately I am still no closer to booting.
In the meantime I flashed my new chip with my OEM firmware backup. It boots; then I flashed my patched IFD (for chip ID and flash unlock) and it still boots. So it's not chip compatibility or corrupted descriptor.
The only sign of life I got is the bootblock banner left in the SPI console. My PCI POST card is showing nothing, but knowing that it sits on a PCIe-PCI bridge (ASM1063 that P8Z77M-PRO does not have) and not knowing if it needs software init to work, I am now trying to pull POST codes off the LPC bus over the TPM header, using an Arduino Due. Do I have to add some early init to have port 80 accesses sent to LPC bus for this to work?
You have to tell coreboot where to route LPC post codes to. It defaults to "None", but you can choose PCI or LPC. I have never tried to print post codes with coreboot, though. I would try using the serial port though, as it is more practical for debugging than post codes.
Thanks for your help Keith _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards,
Angel Pons _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi coreboot folks,
I was unable to get any serial output, even with early serial configured.
Z77 power on defaults will see port 80 decoded by LPC according to their datasheet, and I found Asus actually included with some boards a POST card that plugs into the TPM header, so I'm on the right track. Now to see if I can implement the LPC protocol correctly on an Arduino Due, chosen for its 84MHz clock and 3.3v operation.
I looked at the source and only see the CONFIG_POST_DEVICE_* options used by sb/amd/*/hudson, not by any Intel platform code.
I then looked at the datasheet and the lspci dump with OEM BIOS. I would need to do something to device 0x1e.0 (disabled!) and 0x1c.6 (PCIe root port 6) and I would need new code that connects to CONFIG_POST_DEVICE_*.
I couldn't get LPC bus right on the Due, but I did get serial going. Initially I didn't get anything past the bootblock signon banner, but curiously after inserting a stub bootblock_mainboard_init(), I was able to get serial going and got some logs.
My .config is attached, and the boot log follows. TL;DR: Memory init failed.
The RAM are a pair of Samsung 4GB PC3-12800S-11-11-F3 SODIMM modules on adapters. They did work with OEM firmware. And the adapters have been used elsewhere with no problems.
After replacing the RAM with a pair of OCZ 2GBs I was eventually able to go all the way through SeaBIOS. It probably booted my SystemRescueCD on a USB3 stick too, but I cannot say for sure, with only a black screen throughout out of onboard video.
OCZ boots with both MRC and native RAM init; Samsung SODIMM fails with both.
Where should I look next?
Thanks Keith
--- BEGIN SERIAL LOG --- coreboot-4.11-1091-g3aed3ba60b-dirty Fri Feb 28 04:11:27 UTC 2020 bootblock starting (log level: 8)... bootblock_mainboard_init() [1] FMAP: Found "FLASH" version 1.1 at 0x190000. FMAP: base = 0xff800000 size = 0x800000 #areas = 4 FMAP: area COREBOOT found @ 190200 (6749696 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 132ac BS: bootblock times (exec / console): total (unknown) / 31 ms
--- BEGIN NATIVE RAMINIT LOG --- coreboot-4.11-1091-g3aed3ba60b-dirty Fri Feb 28 04:11:27 UTC 2020 romstage starting (log level: 8)... SMBus controller enabled Setting up static northbridge registers... done Initializing Graphics... Back from systemagent_early_init() POST: 0x38 POST: 0x39 POST: 0x3a Intel ME early init Intel ME firmware is ready ME: Requested 16MB UMA Starting native Platform init DMI: Running at X4 @ 5000MT/s FMAP: area RW_MRC_CACHE found @ 180000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' SPD probe channel0, slot0 SPD probe channel0, slot1 SPD probe channel0, slot0 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0x3 SPD probe channel0, slot1 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0xf SPD probe channel1, slot0 SPD probe channel1, slot1 SPD probe channel1, slot0 SPD probe channel1, slot1 Starting Ivybridge RAM training (0). 100MHz reference clock support: yes Trying CAS 11, tCK 320. Found compatible clock, CAS pair. Selected DRAM frequency: 800 MHz Selected CAS latency : 11T PLL busy... done in 10 us MCU frequency is set at : 800 MHz Selected CWL latency : 8T Selected tRCD : 11T Selected tRP : 11T Selected tRAS : 28T Selected tWR : 12T Selected tFAW : 24T Selected tRRD : 5T Selected tRTP : 6T Selected tWTR : 6T Selected tRFC : 128T Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 2 PCI(0, 0, 0)[bc] = 82a00000 PCI(0, 0, 0)[a8] = 7c600000 PCI(0, 0, 0)[ac] = 2 PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80a00000 PCI(0, 0, 0)[b4] = 80800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = ff000000 PCI(0, 0, 0)[74] = 1 PCI(0, 0, 0)[78] = ff000c00 Done memory map Done io registers Done jedec reset Done MRS commands edge write discovery failed: 0, 0, 2 RAM training failed, trying fallback. SPD probe channel0, slot0 SPD probe channel0, slot1 SPD probe channel0, slot0 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0x3 SPD probe channel0, slot1 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0xf SPD probe channel1, slot0 SPD probe channel1, slot1 SPD probe channel1, slot0 SPD probe channel1, slot1 Starting Ivybridge RAM training (0). No valid DIMMs found --- END NATIVE RAMINIT LOG ---
--- BEGIN MRC RAMINIT LOG --- coreboot-4.11-1091-g3aed3ba60b-dirty Fri Feb 28 04:11:27 UTC 2020 romstage starting (log level: 8)... SMBus controller enabled Setting up static northbridge registers... done Initializing Graphics... Back from systemagent_early_init() POST: 0x38 POST: 0x39 RAMINIT: Limiting DDR3 clock to 800 Mhz POST: 0x3a Intel ME early init Intel ME firmware is ready ME: Requested 16MB UMA Starting UEFI PEI System Agent Read scrambler seed 0x00000000 from CMOS 0x98 Read S3 scrambler seed 0x00000000 from CMOS 0x9c prepare_mrc_cache: invalid seed checksum FMAP: area COREBOOT found @ 190200 (6749696 bytes) CBFS: Locating 'mrc.bin' CBFS: Found @ offset 60fdc0 size 2fc94 System Agent: Starting up... System Agent: Initializing PCH System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USB) System Agent: Initializing PCH (SA Init) System Agent: Initializing PCH (Me UMA) System Agent: Initializing Memory System Agent: failed to locate restore data hob! System Agent: Done. System Agent Version 1.6.0 Build 0 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Normal ME: Current Operation State : Bring up ME: Current Operation Mode : Normal ME: Error Code : No Error ME: Progress Phase : BUP Phase ME: Power Management Event : Moff->Mx wake after an error ME: Progress Phase State : Waiting for DID BIOS message memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00661010): ECC inactive enhanced interleave mode on rank interleave on DIMMA 4096 MB width x8 dual rank, selected DIMMB 4096 MB width x8 dual rank memcfg channel[1] config (00600000): ECC inactive enhanced interleave mode on rank interleave on DIMMA 0 MB width x8 single rank, selected DIMMB 0 MB width x8 single rank MRC_VAR pool occupied [feff7000,feff7110]
--- END MRC RAMINIT LOG ---
[1] This is a message I added in the stub.
Hi Keith
On Sun, Mar 1, 2020 at 9:44 PM Keith Hui buurin@gmail.com wrote:
Hi coreboot folks,
I was unable to get any serial output, even with early serial configured.
Z77 power on defaults will see port 80 decoded by LPC according to their datasheet, and I found Asus actually included with some boards a POST card that plugs into the TPM header, so I'm on the right track. Now to see if I can implement the LPC protocol correctly on an Arduino Due, chosen for its 84MHz clock and 3.3v operation.
I looked at the source and only see the CONFIG_POST_DEVICE_* options used by sb/amd/*/hudson, not by any Intel platform code.
I then looked at the datasheet and the lspci dump with OEM BIOS. I would need to do something to device 0x1e.0 (disabled!) and 0x1c.6 (PCIe root port 6) and I would need new code that connects to CONFIG_POST_DEVICE_*.
I couldn't get LPC bus right on the Due, but I did get serial going. Initially I didn't get anything past the bootblock signon banner, but curiously after inserting a stub bootblock_mainboard_init(), I was able to get serial going and got some logs.
That is good to hear.
My .config is attached, and the boot log follows. TL;DR: Memory init failed.
That is not so good to hear.
The RAM are a pair of Samsung 4GB PC3-12800S-11-11-F3 SODIMM modules on adapters. They did work with OEM firmware. And the adapters have been used elsewhere with no problems.
Alright. That is a rather weird configuration, but I guess it should work.
After replacing the RAM with a pair of OCZ 2GBs I was eventually able to go all the way through SeaBIOS. It probably booted my SystemRescueCD on a USB3 stick too, but I cannot say for sure, with only a black screen throughout out of onboard video.
OCZ boots with both MRC and native RAM init; Samsung SODIMM fails with both.
Uh, interesting. I have seen native raminit fail on some cases, but that MRC also fails is weird.
Where should I look next?
Thanks Keith
--- BEGIN SERIAL LOG ---
<snip>
SPD probe channel0, slot0 SPD probe channel0, slot1 SPD probe channel0, slot0 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0x3 SPD probe channel0, slot1 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0xf SPD probe channel1, slot0 SPD probe channel1, slot1 SPD probe channel1, slot0 SPD probe channel1, slot1 Starting Ivybridge RAM training (0).
Note that only Channel 0 has DIMMs. Channel 1 is completely empty, so you are not using dual channel. Note that having two DIMMs on a single channel is extremely unusual. This means, it is probably not well-tested. Try to put the failing DIMMs on separate channels, and try the slots that are furthest away from the CPU.
100MHz reference clock support: yes Trying CAS 11, tCK 320. Found compatible clock, CAS pair.
<snip>
Done memory map Done io registers Done jedec reset Done MRS commands edge write discovery failed: 0, 0, 2 RAM training failed, trying fallback.
This means that, for some reason, one of the memory training algorithms failed. Native raminit has some weird bugs, but it's hard to fix them given the publicly available documentation (none). The raminit then proceeds to do "fallback" mode, which disables the failing channel and tries again.
SPD probe channel0, slot0 SPD probe channel0, slot1 SPD probe channel0, slot0 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0x3 SPD probe channel0, slot1 Row addr bits : 15 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 4096 MB CAS latencies : 5 6 7 8 9 10 11 tCKmin : 1.250 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 35.000 ns tRCmin : 48.125 ns tRFCmin : 160.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0xf SPD probe channel1, slot0 SPD probe channel1, slot1 SPD probe channel1, slot0 SPD probe channel1, slot1 Starting Ivybridge RAM training (0). No valid DIMMs found
Both DIMMs are on the failing channel. This means that there are no DIMMs to initialize on the other channel, so raminit just halts.
--- END NATIVE RAMINIT LOG ---
--- BEGIN MRC RAMINIT LOG ---
<snip> (MRC raminit debug logs are wet noodles, not really useful)
--- END MRC RAMINIT LOG ---
[1] This is a message I added in the stub.
Best regards,
Angel Pons
-
Angel Pons -
Frans Hendriks -
Keith Hui