r3694 - trunk/util/flashrom

Author: uwe
Date: 2008-10-26 19:40:42 +0100 (Sun, 26 Oct 2008)
New Revision: 3694

Modified:
   trunk/util/flashrom/chipset_enable.c
Log:
Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.

Tested on PIIX3 hardware.

Signed-off-by: Uwe Hermann 
Acked-by: Corey Osgood

Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c	2008-10-25 18:03:50 UTC (rev 3693)
+++ trunk/util/flashrom/chipset_enable.c	2008-10-26 18:40:42 UTC (rev 3694)
@@ -125,6 +125,7 @@

/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
     *            FFF00000-FFF7FFFF are forwarded to ISA).
+	 *            Note: This bit is reserved on PIIX/PIIX3.
     * Set bit 7: Extended BIOS Enable (PCI master accesses to
     *            FFF80000-FFFDFFFF are forwarded to ISA).
     * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
@@ -134,7 +135,10 @@
     * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
     * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
     */
-	new = old | 0x02c4;
+	if (dev->device_id == 0x122e || dev->device_id == 0x7000)
+		new = old | 0x00c4;	/* Bit 9 is reserved on PIIX/PIIX3. */
+	else
+		new = old | 0x02c4;

if (new == old)
    	return 0;
@@ -745,6 +749,8 @@

static const FLASH_ENABLE enables[] = {
    {0x1039, 0x0630, "SiS630",		enable_flash_sis630},
+	{0x8086, 0x122e, "Intel PIIX",		enable_flash_piix4},
+	{0x8086, 0x7000, "Intel PIIX3",		enable_flash_piix4},
    {0x8086, 0x7110, "Intel PIIX4/4E/4M",	enable_flash_piix4},
    {0x8086, 0x7198, "Intel 440MX",		enable_flash_piix4},
    {0x8086, 0x2410, "Intel ICH",		enable_flash_ich_4e},