[coreboot] Erying Tigerlake HM570 Micro-ATX motherboard S3 memory power gate..

[Timothy Potter]

I've been looking at the work being done here
https://github.com/ellyq/coreboot to get coreboot as an alternative to
Erying's flaky BIOS.   I'm particularly interested in getting S3 suspend
working.  From what I can see, the motherboard suspends correctly, but
doesn't maintain power to the DRAM, so resets when it resumes.

Given Erying won't provided schematics for the motherboard, is there any
other way to work out how to "gate" the DRAM power reset signal?  I assume
it's controlled by a GPIO pin on the PCH/CPU.    Are there standard pin
assignments for these signals?    I see some references to it in the
codebase with respect to Lenovo using a different pin.

Thanks,
  Tim.