Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some config issues which prevented the board from booting, I'm left with two issues on which I'm stuck:
1) the internal emmc / sdhci controller fails to initialize, and is unavailable for boot or OS installation 2) video output works properly for SeaBIOS and grub/syslinux, but output is disabled once the OS / kernel driver loads
For the emmc, cbmem shows that the sdhci controller is timing out after setting the initial frequency, somewhere after line 410 of seabios/src/hw/sdcard.c. Since the same exact SeaBIOS payload works properly with the stock ChromeOS firmware (in both the RW_LEGACY and BOOT_STUB slots), I suspect that the issue is with coreboot, but the SoC init is pretty much identical between upstream and NINJA's CrOS branch (save for a few base addresses and offset calculations), so not sure where to start looking. I've also tried putting the sdhci controller back into PCI mode (vs ACPI) which had no effect.
For the video output, the same vgabios file is being used as stock CrOS, and same SeaBIOS payload. The i915 kernel driver reports that no displays are connected, and there are some errors in the drm module just prior. I tested with a few different flavors of linux as well as Windows 10, to be certain it wasn't driver-related.
Attached are the cbmem and kernel logs from both working (stock CroS firmware + upstream SeaBIOS/BOOT_STUB) and non-working (upstream coreboot+SeaBIOS) cases.
As the board hasn't been officially upstreamed yet (something I will do once these issues are resolved), source can be found in my github repo here (it's just 3 commits on top of the current master branch): https://github.com/MattDevo/coreboot/tree/ninja_upstream
Hopefully someone can point me in the right direction here :)
cheers, Matt