Hi,
i should append:
this is using a spi flash with 2 Megs and todays svn version. i also tried with a 1 meg fhw with a somewhat earlier version of coreboot. same problem.
regards,
karl
2010/3/8 Karl-Heinz Nirschl kh.nirschl@googlemail.com:
Hi there,
i'm new to coreboot and trying to port coreboot to a intel core based board. it's a u2500 with a ich7m and 945gm. i started with kontron 986lcd-m which should be quite similar but didn't have much success so far.
the board hangs with post code 0x23 (pci post card) which is bevor "call stage1_main" in model_6ex/cache_as_ram.inc.
as this is very early and the cpu never seem to come to stage1_main (in cache_as_ram_disable.c) i assume i have a problem with my toolchain.
I build on ubuntu 8.04 (Hardy Heron) with nothing special.
Any hints for a coreboot newbie? Which additional information could i provide to find the problem?
Best Regards,
karl