On 3/8/10 6:36 PM, Karl-Heinz Nirschl wrote:
i should append:
this is using a spi flash with 2 Megs and todays svn version.
i also tried with a 1 meg fhw with a somewhat earlier version of
coreboot. same problem.
2010/3/8 Karl-Heinz Nirschl <kh.nirschl(a)googlemail.com>om>:
> Hi there,
> i'm new to coreboot and trying to port coreboot to a intel core based
> board. it's a u2500 with a ich7m and 945gm.
> i started with kontron 986lcd-m which should be quite similar but
> didn't have much success so far.
Did you adapt the code for your SuperIO chip? Do you get any messages on
the serial port?
> the board hangs with post code 0x23 (pci post
card) which is bevor
> "call stage1_main" in model_6ex/cache_as_ram.inc.
> as this is very early and the cpu never seem to come to stage1_main
> (in cache_as_ram_disable.c) i assume i have a problem with my
Try this one:
--- src/northbridge/intel/i945/early_init.c (revision 5196)
+++ src/northbridge/intel/i945/early_init.c (working copy)
@@ -867,7 +867,7 @@
/* Change port80 to LPC */
- RCBA32(GCS) &= (~0x04);
+ //RCBA32(GCS) &= (~0x04);
/* Just do it that way */
RCBA32(0x2010) |= (1 << 10);
Then post codes keep going to PCI instead of LPC and you should see
where it's going.
> I build on ubuntu 8.04 (Hardy Heron) with nothing
> Any hints for a coreboot newbie? Which additional information could i
> provide to find the problem?
You should use the reference toolchain in util/crossgcc
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