Hi. Please,scomeone,add these files to coreboot project (attached archive). I've fount that Asus L1N64 is very similar to Asus M2N-E as hardware (mcp+ite8716f+adt7475) and pcb So I fix m2n-e files for diffrent socket *Socket_F*, add *select DIMM_REGISTERED* , turn on *device pci e.0 on end* I can't read any information from i2c-tools . I have the similar log from Asus M2N-E, I could continue after I replaced memory stick to last dimm. At this board Asus L1n64 two first dimms connect to CPU0,others - to CPU1, I've tried all variants - nothing change. Maybe someone can explain how these two mcp55 aree connected between them to nforce 680a. Scheme of this board,look at attached image
Log from serial, system turned off then coreboot-4.0-2135-gccee625-dirty Thu Mar 22 20:45:03 EDT 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=01 NC node|link=00 busn=40 NC node|link=01 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x2 entering ht_optimize_link pos=0xaa, unfiltered freq_cap=0x8075 pos=0xaa, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 1, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 mcp55_num:01