Hi. Please,scomeone,add these files to coreboot project (attached archive). I&#39;ve fount that Asus L1N64 is very similar to Asus M2N-E as hardware (mcp+ite8716f+adt7475) and pcb<br>So I fix m2n-e files for diffrent socket <b>Socket_F</b>, add <b>select DIMM_REGISTERED</b> , turn on <b>device pci e.0 on end</b><br>
I can&#39;t read any information from i2c-tools<br>. I have the similar log from Asus M2N-E, I could continue after I replaced memory stick to last dimm.<br>At this board Asus L1n64 two first dimms connect to CPU0,others - to CPU1, I&#39;ve tried all variants - nothing change. Maybe someone can explain how these two mcp55 aree connected between them to nforce 680a.<br>
Scheme of this board,look at attached image<br><br>Log from serial, system turned off then<br>coreboot-4.0-2135-gccee625-dirty Thu Mar 22 20:45:03 EDT 2012 starting...<br>*sysinfo range: [000cf000,000cf730]<br>bsp_apicid=0x00<br>
Enabling routing table for node 00 done.<br>Enabling UP settings<br>coherent_ht_finalize<br>done<br>core0 started: <br>started ap apicid: * AP 01started<br><br>SBLink=01<br>NC node|link=00<br>        busn=40<br>NC node|link=01<br>
entering optimize_link_incoherent_ht<br>sysinfo-&gt;link_pair_num=0x2<br>entering ht_optimize_link<br>pos=0xaa, unfiltered freq_cap=0x8075<br>pos=0xaa, filtered freq_cap=0x75<br>pos=0x52, unfiltered freq_cap=0x807f<br>pos=0x52, filtered freq_cap=0x7f<br>
freq_cap1=0x75, freq_cap2=0x7f                                                  <br>dev1 old_freq=0x0, freq=0x6, needs_reset=0x1                                    <br>dev2 old_freq=0x0, freq=0x6, needs_reset=0x1                                    <br>
width_cap1=0x11, width_cap2=0x11                                                <br>dev1 input ln_width1=0x4, ln_width2=0x4                                         <br>dev1 input width=0x1                                                            <br>
dev1 output ln_width1=0x4, ln_width2=0x4                                        <br>dev1 input|output width=0x11                                                    <br>old dev1 input|output width=0x11                                                <br>
dev2 input|output width=0x11                                                    <br>old dev2 input|output width=0x11                                                <br>after ht_optimize_link for link pair 0, reset_needed=0x1                        <br>
entering ht_optimize_link                                                       <br>pos=0x8a, unfiltered freq_cap=0x8075                                            <br>pos=0x8a, filtered freq_cap=0x75                                                <br>
pos=0x52, unfiltered freq_cap=0x807f                                            <br>pos=0x52, filtered freq_cap=0x7f                                                <br>freq_cap1=0x75, freq_cap2=0x7f                                                  <br>
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1                                    <br>dev2 old_freq=0x0, freq=0x6, needs_reset=0x1                                    <br>width_cap1=0x11, width_cap2=0x11                                                <br>
dev1 input ln_width1=0x4, ln_width2=0x4                                         <br>dev1 input width=0x1                                                            <br>dev1 output ln_width1=0x4, ln_width2=0x4                                        <br>
dev1 input|output width=0x11                                                    <br>old dev1 input|output width=0x11                                                <br>dev2 input|output width=0x11                                                    <br>
old dev2 input|output width=0x11                                                <br>after ht_optimize_link for link pair 1, reset_needed=0x1                        <br>after optimize_link_read_pointers_chain, reset_needed=0x1                       <br>
mcp55_num:01 <br><br><br>