From: Scott Duplichan scott@notabs.org
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/agesawrapper.c | 7 ------- src/mainboard/asrock/e350m1/romstage.c | 5 +++++ 2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 9f587b9..e98d874 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -157,13 +157,6 @@ agesawrapper_amdinitmmio ( PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 41f9a6b..4b45caf 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8;
+ // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);