From: Scott Duplichan scott@notabs.org
1) Set I/O APIC ID according to BKDG recommendation 2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/acpi_tables.c | 2 +- src/mainboard/asrock/e350m1/get_bus_conf.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 292aaad..20b0dc2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -64,7 +64,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 9e148d0..5f48498 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -138,7 +138,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */ bus_isa = 10; - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_CPUS; //#if CONFIG_LOGICAL_CPUS==1 // apicid_base = get_apicid_base(1); //#endif diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 78eec6a..e286e6f 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x37) & 0xFF) << 24; - smp_write_ioapic(mc, apicid_sb800, 0x11, dword); + smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00);
From: Scott Duplichan scott@notabs.org
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/agesawrapper.c | 37 ++++++++++++++------------- 1 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 649fcb7..e946a3b 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -85,38 +85,39 @@ agesawrapper_amdinitcpuio ( PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader;
- /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00000B00; + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM-DFFFFFFF to Node0 Link0. */ + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00DFFF00; + PciData = 0x00FECF00; // last address before non-posted range LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); - PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ + + /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000013; + PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); Status = AGESA_SUCCESS; return (UINT32)Status;
From: Scott Duplichan scott@notabs.org
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/agesawrapper.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index e946a3b..4e3819a 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -138,7 +138,8 @@ agesawrapper_amdinitmmio ( Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; + + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
From: Marc Jones marcj303@gmail.com
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge peter@stuge.se --- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 32d4497..ddde158 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
From: Scott Duplichan scott@notabs.org
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/romstage.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index d63fbe8..d761d73 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8;
+ // early enable of SPI 33 MHz fast mode read + if (boot_cpu()) + { + volatile u32 *spiBase = (void *) 0xa0000000; + u32 save; + __outdword (0xcf8, 0x8000a3a0); + save = __indword (0xcfc); + __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base + spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14); + spiBase [0] |= 1 << 18; // fast read enable + __outdword (0xcfc, save); // clear temp base + } + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init();
From: Scott Duplichan scott@notabs.org
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/romstage.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index d761d73..7f0b9df 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8;
+ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) {
From: Scott Duplichan scott@notabs.org
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/romstage.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7f0b9df..41f9a6b 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);
+ // early enable of PrefetchEnSPIFromHost + if (boot_cpu()) + { + __outdword (0xcf8, 0x8000a3b8); + __outdword (0xcfc, __indword (0xcfc) | 1 << 24); + } + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) {
From: Scott Duplichan scott@notabs.org
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/fadt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/fadt.c b/src/mainboard/asrock/e350m1/fadt.c index 165a980..0b37885 100644 --- a/src/mainboard/asrock/e350m1/fadt.c +++ b/src/mainboard/asrock/e350m1/fadt.c @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4);
From: Scott Duplichan scott@notabs.org
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/dsdt.asl | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index ddde158..ce23245 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1379,7 +1379,7 @@ DefinitionBlock (
/* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2)
From: Scott Duplichan scott@notabs.org
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/dsdt.asl | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index ce23245..8dc40d0 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1483,9 +1483,8 @@ DefinitionBlock ( 0xF300 /* length */ )
-#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
From: Scott Duplichan scott@notabs.org
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/buildOpts.c | 24 ++++++++++++------------ 1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index aa32bb0..cde9df7 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -80,16 +80,16 @@ #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE #define BLDOPT_REMOVE_DQS_TRAINING FALSE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE @@ -97,17 +97,17 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_ATM_MODE TRUE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE -//#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
/* @@ -123,7 +123,7 @@ #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
/* * Agesa configuration values selection.
From: Scott Duplichan scott@notabs.org
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/agesawrapper.c | 35 +++++++++++++-------------- 1 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 4e3819a..9f587b9 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -444,33 +444,32 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct = {0}; + AMD_LATE_PARAMS *AmdLateParams;
- LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + return 0; // this causes bad ACPI SSDT, need to debug
- AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdInitLate (&AmdLateParams); + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdCreateStruct (&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate (AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); }
- DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit;
- AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib;
+ AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; }
From: Scott Duplichan scott@notabs.org
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/agesawrapper.c | 7 ------- src/mainboard/asrock/e350m1/romstage.c | 5 +++++ 2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 9f587b9..e98d874 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -157,13 +157,6 @@ agesawrapper_amdinitmmio ( PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 41f9a6b..4b45caf 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,6 +47,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8;
+ // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);
From: Scott Duplichan scott@notabs.org
Signed-off-by: Peter Stuge peter@stuge.se --- src/mainboard/asrock/e350m1/devicetree.cb | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 9dceae6..d1e4a8b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -99,12 +99,12 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 # These seem unnecessary
From: Scott Duplichan scott@notabs.org
Signed-off-by: Peter Stuge peter@stuge.se --- src/mainboard/asrock/e350m1/Kconfig | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 9b73ea3..fdcc3c9 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -22,8 +22,6 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select DIMM_DDR3 - select DIMM_UNREGISTERED select CPU_AMD_AGESA_WRAPPER_FAMILY14 select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 @@ -42,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA
@@ -86,18 +83,6 @@ config MEM_TRAIN_SEQ int default 2
-config SB_HT_CHAIN_ON_BUS0 - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - config IRQ_SLOT_COUNT int default 11
From: Scott Duplichan scott@notabs.org
Signed-off-by: Peter Stuge peter@stuge.se --- src/mainboard/asrock/e350m1/get_bus_conf.c | 18 +----------------- 1 files changed, 1 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 5f48498..cc7fb5d 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -42,25 +42,12 @@ u32 pci1234x[] = { 0x0000ff0, };
-/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - u32 bus_type[256]; - u32 sbdn_sb800;
-//KZ [092110]extern void get_pci1234(void); - static u32 get_bus_conf_done = 0;
- - void get_bus_conf(void) { u32 apicid_base; @@ -139,8 +126,5 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; -//#if CONFIG_LOGICAL_CPUS==1 -// apicid_base = get_apicid_base(1); -//#endif - apicid_sb800 = apicid_base + 0; + apicid_sb800 = apicid_base; }
mbuschman@lucidmachines.com wrote:
From: Scott Duplichan scott@notabs.org
- Set I/O APIC ID according to BKDG recommendation
- Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com
All are either
Acked-by: Peter Stuge peter@stuge.se
or
Acked-by: Marshall Buschman mbuschman@lucidmachines.com
per IRC. Committed as r6621 to r6636.
Many thanks to Scott for these fixes to amd/persimmon, and to Marshall for working on getting them over to asrock/e350m1, which should now be functionally equivalent to amd/persimmon, as has also been tested by Marshall.
//Peter
Peter Stuge wrote:
]All are either ] ]Acked-by: Peter Stuge peter@stuge.se ] ]or ] ]Acked-by: Marshall Buschman mbuschman@lucidmachines.com ] ]per IRC. Committed as r6621 to r6636. ] ]Many thanks to Scott for these fixes to amd/persimmon, and to ]Marshall for working on getting them over to asrock/e350m1, which ]should now be functionally equivalent to amd/persimmon, as has also ]been tested by Marshall. ] ] ]//Peter
Thank you Peter and Marshall. I will keep my e350m1 board around for future testing and experiments.
Thanks, Scott
-
mbuschman＠lucidmachines.com -
Peter Stuge -
Scott Duplichan