Re: [coreboot] [PATCH] New config option for 440BX northbridge

[Rudolf Marek]

Hi,

check design guide 3.4.3 GCKE and DCLKRD/DCLKWR Connection

download.intel.com/design/chipsets/designex/29063401.pdf

Module Mode Configuration (MMCONFIG). This bit is set by an external 
strapping option. The
   combination of this bit and the SDRAMPWR bit (SDRAMC register) determine the 
functioning of
   the CKE signals as defined as follows:
   SDRAMPWR          MMCONFIG        CKE Operation
      0                 0            3 DIMM, CKE[5:0] driven, self-refresh entry 
staggered.
5                                   SDRAM dynamic power down available.
      X                 1            3 DIMM, CKE0 only, self-refresh entry not 
staggered. SDRAM
                                     dynamic power down unavailable.
      1                 0            4 DIMM, GCKE only, self-refresh entry 
staggered. SDRAM
                                     dynamic power down unavailable.
   NOTE: Under MMCONFIG mode, the AGP must be disabled.

download.intel.com/design/chipsets/datashts/29063301.pdf

If you just know this, please disregard this mail

Rudolf