RE: Help NS Geode experts

[Adam Bezanson]

Ahhh thanks, It's working now!!!
Although my kernel isn't starting up.
I'm getting the same thing that was reported to the
list last month about gunzip errors

Welcome to start32, the open sourced starter.
This space will eventually hold more diagnostic information.

January 2000, James Hendricks, Dale Webster, and Ron Minnich.
Version 0.1

200:init_bytes() - zkernel_start:0xfff10000  zkernel_mask:0x0000ffff
Searching for 16 byte tags
    63:rom_read_bytes() - overflowed source buffer. max_block = 14
init_bytes found 0 tags
Gunzip setup
gunzip_setup
output data is 0x00100000
Gunzipping boot code
bad gzip magic numbers

Was the solution ever mentioned? What have I configured wrong?
My kernel? or the zkernel_start address?

Thanks,
Adam

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]]On Behalf Of Steven James
Sent: Wednesday, January 01, 2003 12:23 PM
To: Adam Bezanson
Cc: [e-mail]
Subject: Re: Help NS Geode experts

Greetings,

I'm no Geodeexpert, but perhaps I can help.

Typically at powerup, the adress space at ffff0000 - ffffffff is mapped to
f0000:0000 (top of real mode memory at 1M). The CPU will start up at
f0000:fff0.

The practical upshot is that the end of your romimage should be line up at
ffffffff to get the power on jmp vector in the right place.

G'day,
sjames

Happy New Year LinuxBIOS

Quoting Adam Bezanson :
> Hi guys,
>
> I've finally built linuxbios for my SC1200 based board.
> I've written my own flash programming utility so I can program
> the "romimage" file produced into my flash part from Linux command
> line.
> This all seems to work fine. On my board, I have the ability (with a
> jumper)
> to direct the ROMCS# signal to one of 3 chips on the board. One is a
> Disk on Chip which currently has a DOS filesystem on it, one is a 2Mbit
> flash chip which has the original Insyde BIOS, and the 3rd is a 16Mbit
> flash part soldered on the board where I'm trying to put linuxbios.
>
> This 3rd chip is at 0xffe00000 - 0xffffffff, in order to enable this
> addressing I must hit bit 2 in F0 offset 0x52 to enable the Upper ROM
> size
> based on the ROM Mask at F0 offset 0x6e. This isn't enabled by default
> so
> I think as the chip comes up only 0xfffc0000 - 0xffffffff is visible.
> I'm not 100% sure, but I assume as the chip comes up it starts trying
> to fetch instructions from 0xfffc0000, is this true?
>
> My question is, where should I program the "romimage" file that comes
> out of the build process? It would seem to me that the linuxbios.rom
> part
> would have to
> start at 0xfffc0000.
>
> Other notes: I've set up my PMR and MCR registers correctly for my
> target. I
> figured them
> out by hand and then verified their values when I run with the Insyde
> BIOS.
> So I'm 100% sure
> the values I'm using are correct for my target.
>
> I've set the SCx200_DOCCS_BASE to 0xffe00000 for the moment
> and the CTRL to 0x070007ff
> I'm not sure if the BASE value is correct due to the questions I pose
> above.
>
> All of my efforts have resulted in nothing happening at startup. Nothing
> out
> of the
> serial port nor are the Port 80 codes moving after the board is reset.
>
> Any ideas/help would be appreciated.
>
> Thanks and have a happy new year.
>
> Adam
>
> Linuxbios mailing list
> [e-mail]
> http://www.clustermatic.org/mailman/listinfo/linuxbios

----------------------------steven james, director of research, linux labs

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