Re: [coreboot] [PATCH] flahsrom: fix off-by-one error in erase

[Carl-Daniel Hailfinger]

Hi Jody,

thank you for the patch! We'll commit it in the next few days.
To have a complete audit log, it would be great if you could add a
Signed-off-by tag to your patch (adding that in a reply to this thread
is OK) according to
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure . Thanks.

On 22.01.2009 22:17, Jody McIntyre wrote:
> There appears to be an off-by-one error when using flashrom's erase:
>
> # flashrom -E
> Calibrating delay loop... OK.
> No coreboot table found.
> Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... OK.
> Found chip "SST SST49LF008A" (1024 KB) at physical address 0xfff00000.
> Erasing flash chip... FAILED!
> ERROR at 0x00100000: Expected=0xff, Read=0x00

Regards,
Carl-Daniel