Yes.
#ifndef ENABLE_APIC_EXT_ID #define ENABLE_APIC_EXT_ID 0 #endif
static void enable_apic_ext_id(u8 node) { #if ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?"
u32 val;
val = pci_read_config32(NODE_HT(node), 0x68); val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); pci_write_config32(NODE_HT(node), 0x68, val); #endif }
-----Original Message----- From: Andi Kleen [mailto:ak@muc.de] Sent: Friday, January 07, 2005 1:29 PM To: YhLu Cc: Stefan Reinauer; Ronald G. Minnich; linuxbios@clustermatic.org; discuss@x86-64.org; jamesclv@us.ibm.com; suresh.b.siddha@intel.com; Matt Domsch Subject: Re: Enable apic ext id to use 256 apic id for AMD64
nodeid = lapicid() & 0xf; #if ENABLE_APIC_EXT_ID == 1 enable_apic_ext_id(nodeid); lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) |
(APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
Surely you should at least enable ApicExtBrd too. Otherwise 0xf will send to all CPUs.
-Andi