Re: [coreboot] [v3][patch] Add early MTRR setup

[Corey Osgood]

On Fri, Feb 6, 2009 at 6:26 PM, Peter Stuge  wrote:
> Marc Jones wrote:
> > Setup the MTRRs in stage1 so that memory and cache are available
>
> throughout
> > stage2. This fixes problems with VGA graphics ROMs access to
>
> 0xA0000-0xBFFFF.
> > It also sets all system memory to WriteBack cached and sets the ROM
> > area to cached.
> >
> > Signed-off-by: Marc Jones
>
> Acked-by: Peter Stuge

+    /* System ROM (Assume 1MB) */
> stage1_set_var_mtrr(1, 0xFFF00000, 0x00100000, MTRR_TYPE_WRTHROUGH);

Can we do CONFIG_COREBOOT_ROM_SIZE_KB << 10 instead? Otherwise we'll have
breakage with any rom >1MB.

Thanks,
Corey