coreboot

coreboot@coreboot.org

6 participants
39687 discussions

EFI Payload and coreboot Debug Control
by Rao G 31 Jan '22

31 Jan '22

Hi All, Trying to pass data between EFI Payload and coreboot, my use case is when a setup token is enabled, the data should be read by coreboot and change the DEBUG options in coreboot In EFI Payload values in PcdDebugPropertyMask can be toggled to ON/OFFit Please shed some light onto it Thanks Rao

1 0

T440P
by Patrick Bratu 29 Jan '22

29 Jan '22

Hello dear team of Coreboot I tried to install CoreBoot with SeaBios on my T440p with dGPU but I can not get the graphics card to show up and when installing Arch also always come errors can you help me please? Best Regards

2 1

SPIBAR + 0x10 offset with MMIOREAD32 causing exception
by Rao G 28 Jan '22

28 Jan '22

Hi All, Trying to access SPI Flash from EFI payload 1) SpiInstance->PchSpiBase = MmPciBase ( DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SPI, PCI_FUNCTION_NUMBER_PCH_SPI ); DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase)); >> returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0) 2) ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000; Expectation: this should return value at 0xC00FD010 Result The above code is throwing processor exception PchSpiBase at 0xC00FD000 !!!! X64 Exception Type - 0E(#PF - Page-Fault) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0 RIP - 00000000771903D0, CS - 0000000000000038, RFLAGS - 0000000000010046 Any clues whether SPI flash needs to be enabled in descriptor or any straps by using FIT tool? Thanks Rao

3 7

[coreboot - Bug #312] [Tianocore] gcc11: UefiPayloadPkg build fails
by coreboot＠fe80.eu 28 Jan '22

28 Jan '22

Issue #312 has been updated by Patrik Tesarik. Seems to be fixed? Building works for me again. (Upstream is still broken). Can we close this then? ---------------------------------------- Bug #312: [Tianocore] gcc11: UefiPayloadPkg build fails https://ticket.coreboot.org/issues/312#change-868 * Author: Patrik Tesarik * Status: In Progress * Priority: Normal * Assignee: Matt DeVillier * Category: * Target version: ---------------------------------------- With gcc11 the build of UefiPayloadPkg fails because the brotli code fails. This bug is fixed 'already' today (after 3 Months) in upstream brotli: https://github.com/google/brotli/pull/893 And the issue was already discussed in upstream EDK2, but it seems to me that the submodule reference(?) not fixed yet. https://bugzilla.tianocore.org/show_bug.cgi?id=3417 However, this ticket should make the maintainer of https://github.com/MrChromebox/edk2 aware that a pull of that brotli fix is trickles down somehow. Not sure what's the right way to go here. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

2022-01-26 - coreboot Leadership Meeting Minutes
by coreboot org 26 Jan '22

26 Jan '22

# 2022-01-26 - coreboot Leadership Attendees: Felix Singer, Jay Talbott, Werner Zeh, Tim Crawford, Patrick Georgi, Stefan Reinauer, David Hendricks, Eric Peers, Felix Held, Martin Roth, Daniel Maslowski, j. redpath, Christian Walter, Ron Minnich Agenda / Minutes * [Felix S.] flashrom is looking for mentors * [https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/VADY… * Looking for mentors. If someone is interested in being a mentor, please respond to this mail mentioned above and also send a copy to Anastasia K. [aklm@chromium.org](mailto:aklm@chromium.org). * homepage.git: who should be able to set Verified+1 there? * Right now, only Stefan, Patrick and Martin can. * We could extend this to an existing Gerrit group, e.g. users who can submit coreboot changes, or create a new Gerrit group with this specific permission. * Patrick is created [a new group](https://review.coreboot.org/admin/groups/2a680d10d3cdc6990a84d68d1aa… * Inherits the “Core Developers” group (those with submit rights to coreboot) * Allows adding more website maintainers who are not coreboot submitters easily * [Felix S.] coreboot GSoC participation * [https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/PGKT… * Looking for projects and mentors (see the email above) * [Jay T.] CAR layout for Xeon SP * workaround implemented in coreboot: [https://review.coreboot.org/c/coreboot/+/61164](https://review.coreboot.org… * SysPro and 9esec collaborating on solution and discussing with Intel * LVFS * Suggesting to provide coreboot for older/no longer supported (EOL) devices (postmarket) as an alternative on LVFS * [https://github.com/fwupd/fwupd/wiki/LVFS-Community-Meeting-2022-01-28](http… * Should coreboot.org ship binaries? * No. * Probably best left to folks like Mr. Chromebox * Who would do Lenovo support? Libreboot et al ship binaries * Could make things easier for certain projects like Heads that already use coreboot. * Werner: Instability with eMMC devices * Need initialization, seems to be in scope for coreboot * ITRenew server heading for Martin still not there * Martin is ready (space, cables, …) * [New videoconferencing system?](#bookmark=id.ehzxgz9a1ta0) * Google changed policy to require Googler to allow access for Googler-initiated meeting. * Public version? 1 hour limit? Number of people? * coreboot account? * This seems problematic, but can be worked. It’s free for non-profits, but the SFC is the non-profit, not coreboot. * OSFF’s google meet? * BigBlueButton worked relatively well for most people, though some still seemed to have issues. * Matt - BBB did a poor job of filtering background noise. Not as good from an audio perspective. * Felix - same. Audio is much better in google meet. * Probably no * Jitsi * Tested [https://meet.jit.si/](https://meet.jit.si/) Limits: 100 ppl is free limit * [http://meet.coreboot.org](http://meet.coreboot.org) now exists, too. * Jitsi performed very well compared to all the other open source solutions that we’ve used. * Unfortunately it flopped in the buildbot discussion on Dec. 8 with only 8-10 participants (https://meet.coreboot.org/BuildbotJenkinsReplacement) * Does this work with firefox? * Firefox worked well compared to a couple of years ago. * In the vpub, we ran into a jitsi issue where some people couldn’t hear each other. * Downside: no phone bridges. If we had one or several SIP servers people can call into, we could hook it up (add-on feature on meet.jit.si but available OOTB for custom installs like meet.coreboot.org) * Audio propagation issues on meet.coreboot.org * Should we change videoconferencing systems for the leadership meeting or not? * Ron: projects keep trying to switch and keep coming back to meet. * Not urgent. If Meet gets too aggravating, waiting to join, we can decide at that point. * We're not going to change now. Meet gives consistently good audio and video quality even with a large number of people. We need to choose the defects, and can look again if we get fed up with google meet. * New social media accounts: * [https://mastodon.technology/@coreboot](https://mastodon.technology/@coreboo… * [https://mastodon.technology/@flashrom](https://mastodon.technology/@flashro… * People who want to help promote them, reach out to Felix S. or Patrick G. * Decision making at flashrom * Project should get some structure, not on how the code is being managed but everything around it (e.g. Twitter accounts), who volunteers to reach out to folks? # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting.

1 0

GSoC 2022: Project ideas & call for mentors
by Felix Singer 26 Jan '22

26 Jan '22

Hello coreboot community, We are about to prepare our application for participating in Google Summer of Code 2022 (FAQ [1]). The timeline is published here [2] and Martin and David will help out as co-admin. I have collected some project ideas from different places [3]. Some might not be needed anymore, though. They still require a proper description, a project type (~175 hrs or ~350 hrs) and they are missing a mentor. If you want to make it happen and be a mentor yourself, if you just want to help out and add the missing information or if you have an own project idea, then please reply to this mail on the mailing list and provide the following information: * Title * Project description * Project type (duration, ~175 hrs or ~350 hrs) * Required skills * Required hardware * Mentor If you want to be a mentor, then please check the dates on the timeline [2] and make sure that it works for you. There is also a short [4] and a detailed [5] guide for the responsibilities of a mentor. If you still have any questions, then please contact us. Your GSoC admin, Felix [1] https://developers.google.com/open-source/gsoc/faq [2] https://developers.google.com/open-source/gsoc/timeline [3] https://docs.google.com/document/d/1LU8CTITfqhJU_G_XHwvSkHAQQWed0_FLWPPoBfc… [4] https://developers.google.com/open-source/gsoc/help/responsibilities#mentor… [5] https://google.github.io/gsocguides/mentor

2 1

Fwd: [Lvfs-announce] LVFS Community Meeting: Alternate Branches
by Patrick Georgi 25 Jan '22

25 Jan '22

Might be interesting for a few folks here? ---------- Forwarded message --------- Von: Richard Hughes <hughsient(a)gmail.com> Date: Di., 25. Jan. 2022 um 12:20 Uhr Subject: [Lvfs-announce] LVFS Community Meeting: Alternate Branches To: <lvfs-announce(a)lists.linuxfoundation.org> Hi all, We normally only allow the silicon vendor, the ODM or the OEM to upload firmware for hardware, and only if that entity has legal permission to upload the file to the LVFS. The security model for fwupd relies on standardised registries like USB and PCI, along with immutable DMI information to ensure that only the correct vendors can ship firmware for their own hardware, and nothing else. This strict rule breaks down where the OEM responsible for the hardware considers the device end-of-life and so will no longer receive updates (even for critical security issues). There may also be a situation where there exists an alternate (not provided by the vendor) free software re-implementation of the proprietary firmware, which may be desired for licensing reasons. In these situations we can now allow another legal entity to also upload firmware for the hardware, but with a few restrictions: * The end user must manually and explicitly opt-in to the new firmware stream, perhaps using fwupdmgr switch-branch, with a suitable warning that there is no vendor support available and that the hardware warranty is now invalid. This means that the alternate firmware must set the device branch appropriately without any additional configuration. * The alternate firmware must not ship with any code, binaries or generated assets from the original hardware vendor (perhaps also including trademarks) unless written permission is provided in writing by the original hardware vendor. Some real world examples might be providing a Open Source BCM57xx GPL firmware for Broadcom network hardware, or providing a coreboot system firmware for a long-EOLed Lenovo X220 ThinkPad. In this instance, the LVFS may be the legal entity distributing the firmware, which is actually provided by a trusted contributor who has permissions to upload and hardware to test the update. In other cases another legal entity (like coreboot itself) or an individual trusted contributor may be considered the distributor. In all cases the specifics should be discussed with the LVFS maintainers, as should any concerns by licensors or existing distributors. I've decided to make this functionality the topic of the first LVFS Community Meeting which is happening this Friday at 1700 GMT. See https://github.com/fwupd/fwupd/wiki/LVFS-Community-Meeting-2022-01-28 for instructions. If you would like me to add you to the Google calendar invite please let me know. If you're not comfortable joining the Community Meeting I'm happy to get private feedback via email too. Richard _______________________________________________ LVFS-announce mailing list LVFS-announce(a)lists.linuxfoundation.org https://lists.linuxfoundation.org/mailman/listinfo/lvfs-announce -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

1 0

Memory Down approach Error on intel Denverton board
by Ganesh Kumar C 25 Jan '22

25 Jan '22

Hi , Greetings . We are working on intel c508 intel denverton board . It has a soldered 4GB DDR4 connected to Channel 0 , Dimm 0 . Below are the changes made : 1. We are using harcuvar board as a reference . I have selected * Enable Memory down option in menu config 2. Added spd values file in src/mainboard/intel/harcuvar/spd/spd_filename.hex 3. spd.bn getting generated in CBFS FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 42084 none cpu_microcode_blob.bin 0xa580 microcode 11264 none fallback/ramstage 0xd200 stage 70701 none config 0x1e680 raw 1227 none revision 0x1ebc0 raw 691 none spd.bin 0x1eec0 spd 512 none fallback/dsdt.aml 0x1f100 raw 7791 none fallback/postcar 0x20fc0 stage 21832 none fallback/payload 0x26540 simple elf 656810 none (empty) 0xc6b40 null 6656600 none fspt.bin 0x71fdc0 fsp 4096 none (empty) 0x720e00 null 3992 none fspm.bin 0x721dc0 fsp 589824 none (empty) 0x7b1e00 null 3992 none fsps.bin 0x7b2dc0 fsp 102400 none (empty) 0x7cbe00 null 114584 none bootblock 0x7e7dc0 bootblock 32768 none 4. Tried giving 256 and 512 values CONFIG_DIMM_SPD_SIZE=256 We are using Fitc tool to generate full fw image,getting below error and got stuck after loading the build UMA: ME UMA size set to 0. Isoc is Disabled. SMBus Legacy: SPD Write Disable bit is locked now! SMBus Host: SPD Write Disable bit is locked now! MRC VERSION: 0x950441 MRCDATA Size: 115F1 MRC_SAVE_RESTORE Size: 6F2C SocStepping: 16 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 1 DDR_CURRENT_FREQ: 1 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 1 DDR_CURRENT_FREQ: 1 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 GetSpdData(ch:0) Dimm:0 MemDn=1 Error! Unsuported DDR type: 255 Status = 0x00000001 Any help on this is highly appreciated . Thanks, Ganesh kumar C

3 6

[coreboot - Feature #108] thinkpad x1 carbon gen 1 remaining tasks
by coreboot＠fe80.eu 24 Jan '22

24 Jan '22

Issue #108 has been updated by lx r. I don't have this laptop anymore. ---------------------------------------- Feature #108: thinkpad x1 carbon gen 1 remaining tasks https://ticket.coreboot.org/issues/108#change-867 * Author: lx r * Status: In Progress * Priority: Normal * Assignee: Alexander Couzens * Category: board support * Target version: ---------------------------------------- * ~~SPD based on inteltool for elpida~~ * ~~missing samsung memory (missing a model or find spd data in uefi)~~ * ~~missing hynix memory (missing a model or find spd data in uefi)~~ * test msata port if soldered (missing msata disk) * ~~use pins to differ 4gb and 8gb (prepare, but missing a model to verify)~~ * check why device consumes more power (+ 3W while idle) * do another test run how much is the difference, see if `powertop --auto-tune` works * check if thermal/power/freq MSR are different * check if it's display backlight * check how big is the consumption when turning display off * enable pci/sata link power save -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

Installing coreboot with SeaBIOS
by bernd1-1＠web.de 23 Jan '22

23 Jan '22

Hi. I go through this tutorial: https://doc.coreboot.org/tutorial/part1.html I'm on Step 5 - Configure the build > Check your configuration (optional step): I entered $ make savedefconfig $ cat defconfig I have changed my mind. Now I'd like to install SeaBIOS instead of coreinfo. What do I need to do? How do I change it? Regards, Bernd

10 52

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot