coreboot

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2024-07-10 - coreboot Leadership Meeting Canceled
by mina＠coreboot.org 09 Jul '24

09 Jul '24

Dear community, Please note that tomorrow's coreboot leadership meeting has been canceled because there are no items on the agenda to discuss. Thank you. Best regards, Mina.

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 08 Jul '24

08 Jul '24

Dear coreboot community, At the moment, there are no topics listed on the agenda for the leadership meeting this Wednesday. If there are no additions by the end of the day tomorrow, the meeting would have to be cancelled. If you have any topics you would like to discuss, kindly add them to the agenda items.[1] Thank you. Best regards, Mina. [1](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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Enforcing coreboot as lowercase
by Arthur Heymans 07 Jul '24

07 Jul '24

Hi The coreboot trademark is registered as lowercase. We enforce this in for instance commits, even when normal grammar would dictate uppercase at the start of a sentence. This makes sense for very well known brands, companies and products like "eBay", "iPhone", "AMD". They are all very well known trademarks and they have some uppercase letter in them in atypical places. For these words grammar exceptions seems reasonable. Coreboot is a reasonably well known as a project, but little people know about the specificity of the trademark. This often causes confusion on people either reading "coreboot" at the start of a sense, where it looks grammatically wrong, making it even look unprofessional in the eyes of some. This is because there is no other uppercase letter inside coreboot that would make it a typical exception to regular grammar rules. People getting into the project making the mistake at the start of a sentence, might get the wrong impression of too many idiosyncrasies. On top of that it takes a non zero amount of effort on people in the project to educate others on this trademark thing. Also trademark are typically a bit more broad than exactly how they are registered. I cannot start a company called iNTel or aMD that makes chips. I cannot put a product on the market called "IPHoNE". I think the same applies to "coreboot". So my question is: can we relax the trademark in lowercase enforcement? I would suggest to simply allow both ways. Arthur Heymans

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Question about DISB handling in memory init
by Joursoir 06 Jul '24

06 Jul '24

Hello there, I have been studying the memory initialization process on the Alder Lake platform, like what's going on before and after utilizing FSP-M binary. And while I was studying sources I stumbled upon the following function (src/soc/intel/alderlake/pmutil.c): ``` /* Set the DISB after DRAM init */ void pmc_set_disb(void); ``` It's actually defined in every Intel SoC header and contains SoC-specific implementation. The comment and name function assert that func sets the DISB bit. And yes, it does it. However, I opened Intel 600 Series Chipset Family for IoT Edge Platform Controller Hub (PCH) Datasheet, Volume 2 (dated October 2022, Revision 001) and it asserts the opposite: ``` DRAM Initialization Scratchpad Bit (DISB): <skipped text>. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence. If the bit is 1, then the DRAM initialization was interrupted. ``` So it suggests *clearing* the bit after DRAM init. Why does coreboot do the opposite? I was trying to study git history to find out, but it didn't give me any answer to my question as well. So maybe somebody on the mailing list knows more about it? Is it a typo in the Intel docs? -- Joursoir

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 05 Jul '24

05 Jul '24

Dear community, Please note that our next coreboot leadership meeting is scheduled for Wednesday, July 10,2024.[1] Kindly update the current agenda with matters you wish to see dicussed during the meeting[2] Thank you. Best regards, Mina Asante. [1](https://www.coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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2024-06-26 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 28 Jun '24

28 Jun '24

# 2024-06-26 - coreboot Leadership Meeting ## Attendees Felix Singer, Felix Held, Werner Zeh, Jonathan Hall, David Hendricks, Jay Talbott, Mina Asante, Martin Roth, Karthik Ramasubramanian, Marshall Dawson, Shelley Chen, Maximilian Brune, Lean Sheng Tan. ## Announcements & Events * FOSSY conference: August 1-4 2024 in Portland, Oregon, USA https://sfconservancy.org/fossy * COSCUP - Taipei, Taiwan on 2024/08/03 ~ 2024/08/04 https://coscup.org/2024/en/landing * OSFC will be in Bochum Germany - September 3-5 https://www.osfc.io * OCP Global Summit: San Jose, California on October 15–17, 2024 https://www.opencompute.org/summit/global-summit ## Open Action Items * 2024-05-01 * Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?) * 2024-03-20 * Martin:To Add a note to the gerrit guidelines to email the leadership for further discussion and guidance when code submissions are not up to standard. * 2024-03-06 * Martin: To update gerrit contributing guidelines documentation. (https://doc.coreboot.org/contributing/index.html) * 2024-01-10 * Nico: [https://review.coreboot.org/q/topic:enforce_region_api] * Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. ## Minutes ## Improving coreboot processes ### [Martin] bi-weekly review meetings * In an attempt to get patches merged more quickly, we’re looking at adding a meeting to review patches and try to get blocking issues sorted out. This will start as a bi-weekly meeting of 1 hour and we’ll see where things progress from there. Any preference for Tues/Wed/Thurs? 16:00, 17:00, or 18:00 UTC? (should we define it in UTC or in some other time zone that may switch based on daylight savings?) * 17:00 UTC on Wednesdays opposite the leadership meeting. * David: Start a new google doc to ask for reviews. * Werner: Dedicated email address * Felix: Would it be better to just generate a list? * David: Let’s do both requests and generate a list of patches to review. * Karthik: Should maintainers be involved? * Martin: Absolutely, if they come to the meeting. * David: The idea is to remove bureaucracy * Werner: Who should we invite? * Martin: core devs * Felix: We can change things that don’t work well. ### [Martin] Merge SLOs * Can we define objectives for timeframes to get patches merged to different areas in the codebase? An individual mainboard that doesn’t affect the rest of the codebase doesn’t need as much scrutiny as core code that affects every platform. * Mainboard: 1 week? * FelixH: So what do we do if we get past this timeframe? Just merging anything because it’s passed the SLO period seems like a bad idea. * David: This is designed to help people who are new to the project. We don’t just want to merge stuff, but for isolated code, maybe we can look the other way at imperfections. * FelixH: Frequently add comments and mark as resolved. * David: SoC code still needs to be held to higher standards. * David: We still expect authors to be responsive to feedback. * FelixH: We still need reasonable patches as well - one logical change per patch. * Martin: Do we want any areas besides Mainboards? What about SIOs? * Werner: Maybe drivers? * Max: Everything other than mainboards can be used by multiple vendors? * Martin: It doesn’t seem unreasonable to try to get things merged in a month. * FelixH: It would be good to have a list of things to look at. * Martin: Send out an email with a list of patches which will be looked at in the next meeting? (Yes) * Add a month SLO for drivers & SIOs initially. ### [Karthik] RFC - Extend Coreboot FileSystem to disk * [Extend CBFS to Storage Media](https://docs.google.com/document/d/1LFXIr38_u2bnXY9G6-uJHYxIAFqwX9tU… * Werner: How do we make sure we don’t address the wrong drive? * Karthik: Define a rule in FMAP to describe the characteristic of the disk. * Werner: Wouldn’t coreboot need to search all of the disks? Finding it would be tricky. * Werner: Don’t like searching multiple partitions. * Martin: So would this just be in libpayload * Karthik: The initial code would be just for libpayload. * Martin: I can’t really think of any uses for this in coreboot other than a splash-screen, so I’d really prefer that it just stayed a part of libpayload. * Karthik: We can keep this just a part of libpayload. If we ever need to change that, we can address that again at that point. A notice will be added. * Werner: Last time I dealt with EMMC, there was a difference in speed - training slowed things down and it needed write support. * Martin: I feel like there’s a big difference between training and any writes needed for that, and actually accessing data on the drive. I’m not opposed to the idea of starting training earlier. * David: Are there any patches? * Karthik: I can upload patches in the next week or so - it’ll be a WIP patch. ### [Martin]: Setting aside the reformatting project with clang-format until it’s more stable and has fewer quirks. # Next Leadership Meeting * July 10,2024. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes *[2024-06-26](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit?p).

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 24 Jun '24

24 Jun '24

Dear coreboot community, Please be reminded that our upcoming leadership meeting is on Wednesday, June 26.[1] You are welcome to review and update the current agenda items with any matters you wish to see discussed during the meeting.[2] Below are the items currently on the agenda. ## Current Agenda Items ## Improving coreboot processes ### [Martin] bi-weekly review meetings * In an attempt to get patches merged more quickly, we’re looking at adding a meeting to review patches and try to get blocking issues sorted out. This will start as a bi-weekly meeting of 1 hour and we’ll see where things progress from there. Any preference for Tues/Wed/Thurs? 16:00, 17:00, or 18:00 UTC? (should we define it in UTC or in some other time zone that may switch based on daylight savings?) ### [Martin] Merge SLOs * Can we define objectives for timeframes to get patches merged to different areas in the codebase? An individual mainboard that doesn’t affect the rest of the codebase doesn’t need as much scrutiny as core code that affects every platform. ### [Karthik] RFC - Extend Coreboot FileSystem to disk * [Extend CBFS to Storage Media](https://docs.google.com/document/d/1LFXIr38_u2bnXY9G6-uJHYxIAFqwX9tU…. ## Announcements & Events * FOSSY conference: August 1-4 2024 in Portland, Oregon, USA https://sfconservancy.org/fossy * COSCUP - Taipei, Taiwan on 2024/08/03 ~ 2024/08/04 https://coscup.org/2024/en/landing * OSFC will be in Bochum Germany - September 3-5, 2024 https://www.osfc.io * OCP Global Summit: San Jose, California on October 15–17, 2024 https://www.opencompute.org/summit/global-summit [1](https://www.coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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[coreboot - Support #534] Enable Ethernet (LAN) on ADL-P Custom Board
by Mahesh Kilumu 24 Jun '24

24 Jun '24

Issue #534 has been updated by Mahesh Kilumu. % Done changed from 0 to 100 ---------------------------------------- Support #534: Enable Ethernet (LAN) on ADL-P Custom Board https://ticket.coreboot.org/issues/534#change-1865 * Author: Mahesh Kilumu * Status: New * Priority: Normal * Target version: 4.21 * Start date: 2024-03-21 ---------------------------------------- Hi, With respect to the Alderlake-P RVP platform designed Custom Board. i have been trying to implement the Ethernet(LAN) on my Custom Board. on RVP intel team used GBE PHY but on my custom board we have used the External Realtek RTL8111H controller over PCIe Root port7 for Ethernet. Below are the configuration details: 1) Devicetree.cb: device ref pcie_rp7 on end # Enable PCH PCIE RP 7 using CLK 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, .clk_req = 6, .flags = PCIE_CLK_LAN }" 2) gpio.c: /* 19: PCIE SRCCLKREQ6- same as RVP */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* 2: GPD_2_LAN_WAKE_N- same as RVP*/ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* 21 : LAN_ISOLATE# -New Implementation */ PAD_CFG_GPO(GPP_A21, 1, DEEP), from the logs observed that, Root port got enabled ->> [SPEW ] PCI: 00:00:1c.6: enabled 1 But observed the few Error & warnings in the log with respect to the above configuration [WARN ] Missing root port clock structure definition [ERROR] PCI: 00:00:1c.6 missing read_resources full log details : https://pastebin.com/zWcsEZvL -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 21 Jun '24

21 Jun '24

Dear community, Kindly note that we have an upcoming coreboot leadership meeting scheduled for Wednesday, June 26,2024.[1] We encourage you to take a moment to review the items on the current agenda and share your thoughts or suggest additional matters you wish to see discussed during the meeting.[2] Thank you. Best regards, Mina Asante. [1](https://www.coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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[coreboot - Bug #276] SPI flash console output causes `SMM Handler caused a stack overflow`
by Arthur Heymans 21 Jun '24

21 Jun '24

Issue #276 has been updated by Arthur Heymans. config SMM_MODULE_STACK_SIZE hex default 0x800 if ARCH_RAMSTAGE_X86_64 default 0x400 So just bumping this to always use 0x800 might be a solution ---------------------------------------- Bug #276: SPI flash console output causes `SMM Handler caused a stack overflow` https://ticket.coreboot.org/issues/276#change-1864 * Author: Paul Menzel * Status: New * Priority: Normal * Start date: 2020-07-19 ---------------------------------------- On the Lenovo T60 (Type 2007 with dedicated ATI/AMD graphics device), coreboot built with *SPI Flash console output* (`CONFIG_CONSOLE_SPI_FLASH=y`) fails to boot due to a stack overflow: ``` FMAP: area COREBOOT found @ 60200 (1703424 bytes) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 39300 size 3138 FMAP: area COREBOOT found @ 60200 (1703424 bytes) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at bfb51000. ACPI: * FACS ACPI: * DSDT FMAP: area CONSOLE found @ 0 (131072 bytes) coreboot-4.12-1529-gaba8103093 Sun Jul 19 07:24:18 UTC 2020 smm starting (log level: 7)... canary 0x0 != 0xbfeffc00 SMM Handler caused a stack overflow ``` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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