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QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed
by Mike Banon 21 Feb '24

21 Feb '24

If I use a default config for i440fx/piix4, building a 16MB ROM works fine, but 32MB or 64MB doesn't work anymore: ... CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug OBJCOPY cbfs/fallback/romstage.elf CREATE build/mainboard/emulation/qemu-i440fx/cbfs-file.vqaXlP.out (from /home/my_custom_path_to/coreboot/.config) CC+STRIP src/lib/cbfs_master_header.c OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.elf OBJCOPY bootblock.raw.bin Created CBFS (capacity = 33553892 bytes) BOOTBLOCK CBFS cbfs_master_header CBFS fallback/romstage cbfstool: /home/my_custom_path_to/coreboot/util/cbfstool/cbfstool.c:1145: cbfstool_convert_mkstage: Assertion `IS_HOST_SPACE_ADDRESS(host_space_address)' failed. make: *** [Makefile.inc:1116: build/coreboot.pre] Aborted -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

6 11

coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 19 Feb '24

19 Feb '24

Dear community, Please note that the upcoming coreboot leadership meeting is scheduled for next Wednesday, February 21, 2024.[1] You are welcome to update the current agenda items with matters you wish to see addressed during the meeting.[2] ## Current Agenda Items ### We’ve switched to BigBlueButton for this meeting. * https://bbb.sfconservancy.org/b/mar-sfn-e22-axi * For phone access, call +1-718-247-9666, then enter 89421 as the conference PIN number. * It looks like there’s only a USA phone number. * I found some apps, but they seem to be to run the meeting, not to join it. * See the coreboot calendar for times and more information ### [FelixH] Look at the type that we should be using for readXX * Currently we’ve been using void*, but it’s been argued that using an uintptr_t would be preferable. * Should we use ‘_Generic’? * We’d like to have just a single type. ### [Nico] Revoking Gerrit privileges as punishment. I would like to discuss two matters about this. Not sure about the order. * My own case: I was removed from the core developers and reviewers groups 20 months ago. Without any charge nor chance to defend myself. There was Stefan's sentence, a discrediting rant about me with accusations that fit me not more than many other people, and an offer to reduce the sentence to a month if I were willing to come to the table. Which didn't make sense because I reached out to people long before Stefan's mail and it took Stefan, not me, over three months "to come to the table". And then he still couldn't tell me what I did worse than others. I asked again, Werner this time, what my charge is in 2023, again without results. And now I'm asking again. How can we make things better when we can't even say what was wrong? * [Martin] These issues are not discussed in a public forum where everyone with a pitchfork can get involved. That’s not useful. If you feel that the issues which led to this action being taken have changed, please email all the members of the leadership. Matt, Werner, and David. * Should we use Gerrit privileges as punishment at all? If so, shouldn't we have rules about it? * We will add this to the code of conduct page: ``` As a part of running the project, coreboot leadership has the right to revoke privileges as they see fit. This is not done lightly. Over the history of the coreboot project, there have been only a handful of times where an action needed to be taken. Discussions about these actions are not done publicly, for obvious reasons. If someone believes that the circumstances that led to an action have changed, please send an email to all the members of the leadership team for discussion. ``` * I will note that this text is already there: ``` If a community member engages in unacceptable behavior, the community organizers may take any action they deem appropriate, up to and including a temporary ban or permanent expulsion from the community without warning (and without refund in the case of a paid event). ``` * https://doc.coreboot.org/community/code_of_conduct.html * Doesn't it hurt the project more when it loses a reviewer? (who can still get their own patches merged anyway). * [Martin] I’d say yes, and that’s something that the leadership group has to weigh when they decide to take an action against an individual. * [David] Yes, it does hurt the project when it loses a reviewer (or any contributor, for that matter). That's why it's important to deal with "toxic developers" effectively - to prevent others from leaving the project. No one developer is worth several others who will refuse to work with them. * Should we maybe do the opposite? don't merge their patches unless they do review? * [Martin] When the issue is something other than the quality of a person’s code, it doesn’t make sense to punish them by refusing to allow their patches to be merged. As many people in the community have jobs where they’re required to push code to coreboot, that could be the equivalent to getting them fired, which seems unfair. * If we want to use such punishment, should we apply it to other privileges as well? e.g. administrators, leadership members (IMO very important for trust inside the community) * [Martin] If two members of the leadership voted to take action against a third member, that’s completely allowed. The leadership team can take action as needed. I’ll note that I myself had submit rights taken away for a year. Yes, I’m one of the handful of cases mentioned. ### [Martin] Remove ChromeEC as a submodule - reimplement like a payload * The ChromeEC can currently be built (for some platforms) as a part of the coreboot build. It’s being downloaded as a submodule right now, but this creates a number of issues. With the change to Zephyr, the build process and requirements have changed. To address this, I’d like to propose that we drop the ChromeEC as a submodule, which restricts us to a single version of the code which can be used across all mainboards. With an implementation similar to what’s done for the payloads, the ChromeEC can still be pulled down by platforms which want to build it, and each platform can select a different commit if needed. ### [Martin] Drop Tioga-pass & Xeon-sp? * Marc gave these both +2, so I’m inclined to believe they should be removed, as he was one of the significant contributors, but I’d like to get everyone’s input. “The platform code depends on unreleased binary files and uses incomplete public header files.” https://review.coreboot.org/c/coreboot/+/80171 https://review.coreboot.org/c/coreboot/+/80172 Should they be removed immediately as incomplete and unlikely to be finished? ### 24.02 release * The release tag was done on Monday the 19th. * The announcement will be done on Monday 2024_02_26. * Next release is 24.05. [1](https://coreboot.org/calendar.html). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

4 3

[coreboot - Bug #524] (New) `CONFIG_X2APIC_ONLY=y`or `CONFIG_X2APIC_RUNTIME=y` cause Linux in emulation/qemu-i440fx to crash
by Paul Menzel 19 Feb '24

19 Feb '24

Issue #524 has been reported by Paul Menzel. ---------------------------------------- Bug #524: `CONFIG_X2APIC_ONLY=y`or `CONFIG_X2APIC_RUNTIME=y` cause Linux in emulation/qemu-i440fx to crash https://ticket.coreboot.org/issues/524 * Author: Paul Menzel * Status: New * Priority: Normal * Target version: none * Start date: 2024-02-04 * Affected versions: 4.21 ---------------------------------------- Build coreboot for `emulation/qemu-i440fx` with `CONFIG_X2APIC_ONLY=y`or `CONFIG_X2APIC_RUNTIME=y` causes Linux to crash: ### `CONFIG_X2APIC_ONLY=y` ``` $ qemu-system-x86_64 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22 WARNING: Image format was not specified for '/dev/shm/debian-32.img' and probing guessed raw. Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted. Specify the 'raw' format explicitly to remove the restrictions. [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 bootblock starting (log level: 7)... [INFO ] Timestamp - end of bootblock: 18374588 [INFO ] Timestamp - start of romstage: 20847149 [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x3ffff000 254 entries. [DEBUG] IMD: root @ 0x3fffec00 62 entries. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x0. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: mcache @0x00014e00 built for 13 files, used 0x294 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/postcar' @0x1c140 size 0x91b0 in mcache @0x00014fe0 [DEBUG] Loading module at 0x3ffce000 with entry 0x3ffce042. filesize: 0x7d90 memsize: 0xe118 [DEBUG] Processing 636 relocs. Offset value of 0x3dfce000 [INFO ] Timestamp - end of romstage: 69275568 [DEBUG] BS: bootblock times (exec / console): total (unknown) / 12 ms [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 postcar starting (log level: 7)... [INFO ] Timestamp - start of postcar: 113911520 [INFO ] Timestamp - end of postcar: 117105771 [INFO ] Timestamp - starting to load ramstage: 121657944 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0xd040 size 0xf072 in mcache @0x3fffeaec [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 133785778 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 158178845 [DEBUG] Loading module at 0x3fe9d000 with entry 0x3fe9d000. filesize: 0x234e0 memsize: 0x12fe28 [DEBUG] Processing 3390 relocs. Offset value of 0x3be9d000 [INFO ] Timestamp - finished loading ramstage: 193391473 [DEBUG] BS: postcar times (exec / console): total (unknown) / 5 ms [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 ramstage starting (log level: 7)... [INFO ] Timestamp - start of ramstage: 216358307 [INFO ] Timestamp - device enumeration: 219906562 [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 1 ms [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [DEBUG] PCI: 00:00:00.0 [8086/1237] enabled [DEBUG] PCI: 00:00:01.0 [8086/7000] enabled [DEBUG] PCI: 00:00:01.1 [8086/7010] enabled [DEBUG] PCI: 00:00:01.3 [8086/7113] enabled [DEBUG] PCI: 00:00:02.0 [1234/1111] enabled [DEBUG] PCI: 00:00:03.0 [8086/100e] enabled [DEBUG] PCI: 00:00:01.0 scanning... [DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 0 msecs [DEBUG] PCI: 00:00:01.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:01.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 14 msecs [DEBUG] scan_bus: bus Root Device finished in 18 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 21 ms [INFO ] Timestamp - device configuration: 298893234 [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] QEMU: e820/res: 0xfeffc000 +0x00004000 [DEBUG] QEMU: e820/ram: 0x00000000 + 0x40000000 [DEBUG] QEMU: reserve ioports 0x0510-0x0511 [firmware-config] [DEBUG] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] [DEBUG] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] [DEBUG] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] [DEBUG] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0d base 00000510 limit 00000511 io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0e base 00005658 limit 00005658 io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0f base 0000ae00 limit 0000ae0f io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 10 base 0000af00 limit 0000af1f io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 11 base 0000afe0 limit 0000afe3 io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 01 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.3 01 base 0000e400 limit 0000e43f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.3 02 base 00000f00 limit 00000f0f io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: 4658, Tag: 100 [INFO ] * Base: 5659, Size: 57a7, Tag: 100 [INFO ] * Base: ae10, Size: f0, Tag: 100 [INFO ] * Base: af20, Size: c0, Tag: 100 [INFO ] * Base: afe4, Size: 341c, Tag: 100 [INFO ] * Base: e440, Size: 1bc0, Tag: 100 [DEBUG] PCI: 00:00:03.0 14 * [0xffc0 - 0xffff] limit: ffff io [DEBUG] PCI: 00:00:01.1 20 * [0xffb0 - 0xffbf] limit: ffbf io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 40000000 size: 0 align: 0 gran: 0 limit: fdffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: ffffffffff [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0a base feffc000 limit feffffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0b base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0c base 000c0000 limit 3fffffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 12 base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 13 base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 02 base fec00000 limit fecfffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 03 base fee00000 limit fee0ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base 00008000 limit 0000dfff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 02 base ff800000 limit ffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 03 base fec00000 limit fec00fff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 40000000, Size: be000000, Tag: 200 [INFO ] * Base: 100000000, Size: ff00000000, Tag: 200 [DEBUG] PCI: 00:00:02.0 10 * [0xfd000000 - 0xfdffffff] limit: fdffffff prefmem [DEBUG] PCI: 00:00:03.0 30 * [0xfcfc0000 - 0xfcffffff] limit: fcffffff mem [DEBUG] PCI: 00:00:03.0 10 * [0xfcfa0000 - 0xfcfbffff] limit: fcfbffff mem [DEBUG] PCI: 00:00:02.0 30 * [0xfcf90000 - 0xfcf9ffff] limit: fcf9ffff mem [DEBUG] PCI: 00:00:02.0 18 * [0xfcf8f000 - 0xfcf8ffff] limit: fcf8ffff mem [DEBUG] DOMAIN: 00000000 mem: base: 40000000 size: 0 align: 0 gran: 0 limit: fdffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: ffffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [DEBUG] PCI: 00:00:01.1 20 <- [0x000000000000ffb0 - 0x000000000000ffbf] size 0x00000010 gran 0x04 io [DEBUG] PCI: 00:00:02.0 10 <- [0x00000000fd000000 - 0x00000000fdffffff] size 0x01000000 gran 0x18 prefmem [DEBUG] PCI: 00:00:02.0 18 <- [0x00000000fcf8f000 - 0x00000000fcf8ffff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:02.0 30 <- [0x00000000fcf90000 - 0x00000000fcf9ffff] size 0x00010000 gran 0x10 romem [DEBUG] PCI: 00:00:03.0 10 <- [0x00000000fcfa0000 - 0x00000000fcfbffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:00:03.0 14 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:00:03.0 30 <- [0x00000000fcfc0000 - 0x00000000fcffffff] size 0x00040000 gran 0x12 romem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 5 / 126 ms [INFO ] Timestamp - device enable: 684358641 [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 cmd <- 00 [DEBUG] PCI: 00:00:01.0 cmd <- 00 [DEBUG] PCI: 00:00:01.1 cmd <- 01 [DEBUG] PCI: 00:00:01.3 cmd <- 00 [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:03.0 cmd <- 03 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 2 / 7 ms [DEBUG] BS: BS_DEV_INIT entry times (exec / console): 2 / 0 ms [INFO ] Timestamp - device initialization: 727416775 [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] CPU: QEMU Virtual CPU version 2.5+. [INFO ] LAPIC 0x0 switched to X2APIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x1b8 memsize: 0x1b8 [DEBUG] Processing 17 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 1 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [INFO ] LAPIC 0x1 switched to X2APIC mode. [DEBUG] done. [INFO ] AP: slot 1 apic_id 1 [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #1 initialized [INFO ] bsp_do_flight_plan done after 7 msecs. [DEBUG] CPU_CLUSTER: 0 init finished in 30 msecs [DEBUG] PCI: 00:00:00.0 init [DEBUG] Assigning IRQ 10 to PCI: 00:00:01.3 [DEBUG] Assigning IRQ 11 to PCI: 00:00:03.0 [DEBUG] PCI: 00:00:00.0 init finished in 7 msecs [DEBUG] PCI: 00:00:01.0 init [DEBUG] RTC Init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x02 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [DEBUG] PCI: 00:00:01.0 init finished in 5 msecs [DEBUG] PCI: 00:00:01.1 init [DEBUG] IDE: Primary interface: on [DEBUG] IDE: Secondary interface: on [DEBUG] IDE: Access to legacy IDE ports: off [DEBUG] PCI: 00:00:01.1 init finished in 3 msecs [DEBUG] PCI: 00:00:02.0 init [DEBUG] PCI: 00:00:02.0 init finished in 35 msecs [DEBUG] PCI: 00:00:03.0 init [DEBUG] PCI: 00:00:03.0 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 57 / 43 ms [INFO ] Finalize devices... [INFO ] Devices finalized [INFO ] Timestamp - device setup done: 1027392332 [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms [INFO ] Timestamp - cbmem post: 1037915018 [DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 1 ms [INFO ] Timestamp - write tables: 1046578108 [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. [INFO ] Copying Interrupt Routing Table to 0x3fe93000... done. [DEBUG] PIRQ table: 128 bytes. [INFO ] QEMU: firmware config: Found 'etc/table-loader' [DEBUG] QEMU: found ACPI tables in fw_cfg. [INFO ] QEMU: firmware config: Found 'etc/acpi/rsdp' [DEBUG] QEMU: loading "etc/acpi/rsdp" to 0x3fe6f000 (len 20) [INFO ] QEMU: firmware config: Found 'etc/acpi/tables' [DEBUG] QEMU: loading "etc/acpi/tables" to 0x3fe6f040 (len 131072) [DEBUG] QEMU: loaded ACPI tables from fw_cfg. [DEBUG] Looking on 0x3fe6f000 for valid checksum [DEBUG] Checksum 1 passed [DEBUG] Checksum 2 passed all OK [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] ACPI: * SSDT [DEBUG] Found 2 CPU(s). [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] ACPI tables: 131136 bytes. [DEBUG] smbios_write_tables: 3fe67000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.22-671-g416cc665929e' [DEBUG] SMBIOS: Unknown CPU or CPU doesn't support Deterministic Cache CPUID leaf [INFO ] DOMAIN: 00000000 (QEMU Northbridge i440fx) [INFO ] QEMU: firmware config: Found 'etc/smbios/smbios-tables' [DEBUG] QEMU: found smbios tables in fw_cfg (len 327). [DEBUG] QEMU: coreboot type0 table found at 0x3fe67040. [DEBUG] QEMU: loading smbios tables to 0x3fe67086 [DEBUG] SMBIOS tables: 461 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7ff5 [DEBUG] Writing coreboot table at 0x3fe94000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-0000000000007fff: RAM [DEBUG] 2. 0000000000008000-000000000000dfff: RESERVED [DEBUG] 3. 000000000000e000-000000000009ffff: RAM [DEBUG] 4. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 5. 0000000000100000-000000003fe66fff: RAM [DEBUG] 6. 000000003fe67000-000000003fe9cfff: CONFIGURATION TABLES [DEBUG] 7. 000000003fe9d000-000000003ffccfff: RAMSTAGE [DEBUG] 8. 000000003ffcd000-000000003fffffff: CONFIGURATION TABLES [DEBUG] 9. 00000000fec00000-00000000fec00fff: RESERVED [DEBUG] 10. 00000000ff800000-00000000ffffffff: RESERVED [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [DEBUG] Wrote coreboot table at: 0x3fe94000, 0x310 bytes, checksum 85a4 [DEBUG] coreboot table: 808 bytes. [DEBUG] IMD ROOT 0. 0x3ffff000 0x00001000 [DEBUG] IMD SMALL 1. 0x3fffe000 0x00001000 [DEBUG] CONSOLE 2. 0x3ffde000 0x00020000 [DEBUG] TIME STAMP 3. 0x3ffdd000 0x00000910 [DEBUG] AFTER CAR 4. 0x3ffcd000 0x00010000 [DEBUG] RAMSTAGE 5. 0x3fe9c000 0x00131000 [DEBUG] COREBOOT 6. 0x3fe94000 0x00008000 [DEBUG] IRQ TABLE 7. 0x3fe93000 0x00001000 [DEBUG] ACPI 8. 0x3fe6f000 0x00024000 [DEBUG] SMBIOS 9. 0x3fe67000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x3fffec00 0x00000400 [DEBUG] RO MCACHE 1. 0x3fffe960 0x00000294 [DEBUG] FMAP 2. 0x3fffe8a0 0x000000b6 [DEBUG] ROMSTG STCK 3. 0x3fffe800 0x00000088 [INFO ] Timestamp - finalize chips: 1281447080 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 4 / 77 ms [INFO ] Timestamp - starting to load payload: 1287927356 [INFO ] CBFS: Found 'fallback/payload' @0x25340 size 0x10049 in mcache @0x3fffeb84 [DEBUG] Checking segment from ROM address 0xffc2556c [DEBUG] Checking segment from ROM address 0xffc25588 [DEBUG] Loading segment from ROM address 0xffc2556c [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x00100000 memsize 0x135a30 srcaddr 0xffc255a4 filesize 0x10011 [DEBUG] Loading Segment: addr: 0x00100000 memsz: 0x0000000000135a30 filesz: 0x0000000000010011 [DEBUG] using LZMA [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 1321754094 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 1342389486 [DEBUG] Clearing Segment: addr: 0x000000000011eb68 memsz: 0x0000000000116ec8 [DEBUG] Loading segment from ROM address 0xffc25588 [DEBUG] Entry Point 0x00100000 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 6 / 19 ms [DEBUG] Jumping to boot code at 0x00100000(0x3fe94000) [INFO ] Timestamp - selfboot jump: 1370405009 coreboot: 4.22-671-g416cc665929e FILO version 0.6.0 (pmenzel@abreu) Sun Feb 4 13:23:12 UTC 2024 Press <Enter> for default boot, or <Esc> for boot prompt... timed out boot: hda1:/vmlinuz initrd=hda1:/initrd.img root=/dev/sda1 ro quiet console=ttyS0,115200 ATA-0: [io ports 0x1f0-0x1f7,0x3f6] * hda [ATA Disk]: QEMU HARDDISK Found Linux version 5.6.0-1-686-pae (debian-kernel(a)lists.debian.org) #1 SMP Debian 5.6.7-1 (2020-04-29) relocatable bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... [ 0.051519] kernel BUG at arch/x86/kernel/apic/apic.c:1629! [ 0.052720] invalid opcode: 0000 [#1] SMP PTI [ 0.053664] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.6.0-1-686-pae #1 Debian 5.6.7-1 [ 0.055428] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 4.22-671-g416cc665929e 02/02/2024 [ 0.057435] EIP: setup_local_APIC+0x478/0x4b0 [ 0.058334] Code: fe ff ff 85 d2 0f 8f bd 11 00 00 a1 e0 06 93 df ba 00 07 01 00 8b 48 08 b8 50 03 00 00 e8 20 92 6f 00 e9 db fe ff ff 8d 76 00 <0f> 0b 8d b6 00 00 00 00 0f 0b e9 4b fc ff ff e8 d4 4b 02 00 a1 e0 [ 0.061881] EAX: 00000000 EBX: 00000000 ECX: 00000000 EDX: ffffffff [ 0.063022] ESI: dfaac8cd EDI: 00000000 EBP: df993f64 ESP: df993f14 [ 0.064306] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 [ 0.065936] CR0: 80050033 CR2: ff9ff000 CR3: 1fb48000 CR4: 000006b0 [ 0.066869] Call Trace: [ 0.067243] ? vprintk_default+0x17/0x20 [ 0.067871] ? kvm_arch_para_features+0x43/0x80 [ 0.068468] apic_intr_mode_init+0xf4/0x10a [ 0.069017] x86_late_time_init+0x1d/0x24 [ 0.069544] start_kernel+0x3f9/0x4ac [ 0.070027] i386_start_kernel+0x48/0x4a [ 0.070543] startup_32_smp+0x164/0x168 [ 0.071118] Modules linked in: [ 0.071619] ---[ end trace 61fac992e46bca1b ]--- [ 0.072257] EIP: setup_local_APIC+0x478/0x4b0 [ 0.072850] Code: fe ff ff 85 d2 0f 8f bd 11 00 00 a1 e0 06 93 df ba 00 07 01 00 8b 48 08 b8 50 03 00 00 e8 20 92 6f 00 e9 db fe ff ff 8d 76 00 <0f> 0b 8d b6 00 00 00 00 0f 0b e9 4b fc ff ff e8 d4 4b 02 00 a1 e0 [ 0.075365] EAX: 00000000 EBX: 00000000 ECX: 00000000 EDX: ffffffff [ 0.076426] ESI: dfaac8cd EDI: 00000000 EBP: df993f64 ESP: df993f14 [ 0.077327] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 [ 0.078485] CR0: 80050033 CR2: ff9ff000 CR3: 1fb48000 CR4: 000006b0 [ 0.079731] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.081327] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- ``` ### `CONFIG_X2APIC_RUNTIME=y` ``` $ qemu-system-x86_64 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22 WARNING: Image format was not specified for '/dev/shm/debian-32.img' and probing guessed raw. Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted. Specify the 'raw' format explicitly to remove the restrictions. [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 bootblock starting (log level: 7)... [INFO ] Timestamp - end of bootblock: 16577474 [INFO ] Timestamp - start of romstage: 18671246 [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x3ffff000 254 entries. [DEBUG] IMD: root @ 0x3fffec00 62 entries. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x0. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: mcache @0x00014e00 built for 13 files, used 0x294 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/postcar' @0x1c280 size 0x91b0 in mcache @0x00014fe0 [DEBUG] Loading module at 0x3ffce000 with entry 0x3ffce042. filesize: 0x7d90 memsize: 0xe118 [DEBUG] Processing 636 relocs. Offset value of 0x3dfce000 [INFO ] Timestamp - end of romstage: 67022354 [DEBUG] BS: bootblock times (exec / console): total (unknown) / 21 ms [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 postcar starting (log level: 7)... [INFO ] Timestamp - start of postcar: 90003960 [INFO ] Timestamp - end of postcar: 93116574 [INFO ] Timestamp - starting to load ramstage: 95752126 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0xd040 size 0xf1b6 in mcache @0x3fffeaec [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 134002537 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 159465672 [DEBUG] Loading module at 0x3fe9c000 with entry 0x3fe9c000. filesize: 0x239e0 memsize: 0x130328 [DEBUG] Processing 3412 relocs. Offset value of 0x3be9c000 [INFO ] Timestamp - finished loading ramstage: 173672609 [DEBUG] BS: postcar times (exec / console): total (unknown) / 25 ms [NOTE ] coreboot-4.22-671-g416cc665929e Fri Feb 02 20:40:20 UTC 2024 x86_64 ramstage starting (log level: 7)... [INFO ] Timestamp - start of ramstage: 212046129 [INFO ] Timestamp - device enumeration: 215792182 [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 1 ms [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [DEBUG] PCI: 00:00:00.0 [8086/1237] enabled [DEBUG] PCI: 00:00:01.0 [8086/7000] enabled [DEBUG] PCI: 00:00:01.1 [8086/7010] enabled [DEBUG] PCI: 00:00:01.3 [8086/7113] enabled [DEBUG] PCI: 00:00:02.0 [1234/1111] enabled [DEBUG] PCI: 00:00:03.0 [8086/100e] enabled [DEBUG] PCI: 00:00:01.0 scanning... [DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 0 msecs [DEBUG] PCI: 00:00:01.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:01.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 14 msecs [DEBUG] scan_bus: bus Root Device finished in 18 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 21 ms [INFO ] Timestamp - device configuration: 293163829 [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] QEMU: e820/res: 0xfeffc000 +0x00004000 [DEBUG] QEMU: e820/ram: 0x00000000 + 0x40000000 [DEBUG] QEMU: reserve ioports 0x0510-0x0511 [firmware-config] [DEBUG] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] [DEBUG] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] [DEBUG] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] [DEBUG] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0d base 00000510 limit 00000511 io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0e base 00005658 limit 00005658 io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0f base 0000ae00 limit 0000ae0f io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 10 base 0000af00 limit 0000af1f io (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 11 base 0000afe0 limit 0000afe3 io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 01 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.3 01 base 0000e400 limit 0000e43f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.3 02 base 00000f00 limit 00000f0f io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: 4658, Tag: 100 [INFO ] * Base: 5659, Size: 57a7, Tag: 100 [INFO ] * Base: ae10, Size: f0, Tag: 100 [INFO ] * Base: af20, Size: c0, Tag: 100 [INFO ] * Base: afe4, Size: 341c, Tag: 100 [INFO ] * Base: e440, Size: 1bc0, Tag: 100 [DEBUG] PCI: 00:00:03.0 14 * [0xffc0 - 0xffff] limit: ffff io [DEBUG] PCI: 00:00:01.1 20 * [0xffb0 - 0xffbf] limit: ffbf io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 40000000 size: 0 align: 0 gran: 0 limit: fdffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: ffffffffff [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0a base feffc000 limit feffffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0b base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 0c base 000c0000 limit 3fffffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 12 base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 13 base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 02 base fec00000 limit fecfffff mem (fixed) [DEBUG] avoid_fixed_resources: DOMAIN: 00000000 03 base fee00000 limit fee0ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base 00008000 limit 0000dfff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 02 base ff800000 limit ffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:01.0 03 base fec00000 limit fec00fff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 40000000, Size: be000000, Tag: 200 [INFO ] * Base: 100000000, Size: ff00000000, Tag: 200 [DEBUG] PCI: 00:00:02.0 10 * [0xfd000000 - 0xfdffffff] limit: fdffffff prefmem [DEBUG] PCI: 00:00:03.0 30 * [0xfcfc0000 - 0xfcffffff] limit: fcffffff mem [DEBUG] PCI: 00:00:03.0 10 * [0xfcfa0000 - 0xfcfbffff] limit: fcfbffff mem [DEBUG] PCI: 00:00:02.0 30 * [0xfcf90000 - 0xfcf9ffff] limit: fcf9ffff mem [DEBUG] PCI: 00:00:02.0 18 * [0xfcf8f000 - 0xfcf8ffff] limit: fcf8ffff mem [DEBUG] DOMAIN: 00000000 mem: base: 40000000 size: 0 align: 0 gran: 0 limit: fdffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: ffffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [DEBUG] PCI: 00:00:01.1 20 <- [0x000000000000ffb0 - 0x000000000000ffbf] size 0x00000010 gran 0x04 io [DEBUG] PCI: 00:00:02.0 10 <- [0x00000000fd000000 - 0x00000000fdffffff] size 0x01000000 gran 0x18 prefmem [DEBUG] PCI: 00:00:02.0 18 <- [0x00000000fcf8f000 - 0x00000000fcf8ffff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:02.0 30 <- [0x00000000fcf90000 - 0x00000000fcf9ffff] size 0x00010000 gran 0x10 romem [DEBUG] PCI: 00:00:03.0 10 <- [0x00000000fcfa0000 - 0x00000000fcfbffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:00:03.0 14 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:00:03.0 30 <- [0x00000000fcfc0000 - 0x00000000fcffffff] size 0x00040000 gran 0x12 romem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 6 / 125 ms [INFO ] Timestamp - device enable: 679631328 [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 cmd <- 00 [DEBUG] PCI: 00:00:01.0 cmd <- 00 [DEBUG] PCI: 00:00:01.1 cmd <- 01 [DEBUG] PCI: 00:00:01.3 cmd <- 00 [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:03.0 cmd <- 03 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 5 / 8 ms [DEBUG] BS: BS_DEV_INIT entry times (exec / console): 3 / 0 ms [INFO ] Timestamp - device initialization: 735362458 [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] CPU: QEMU Virtual CPU version 2.5+. [INFO ] LAPIC 0x0 switched to X2APIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x1b8 memsize: 0x1b8 [DEBUG] Processing 17 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 1 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [INFO ] LAPIC 0x1 switched to X2APIC mode. [DEBUG] done. [INFO ] AP: slot 1 apic_id 1 [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #1 initialized [INFO ] bsp_do_flight_plan done after 7 msecs. [DEBUG] CPU_CLUSTER: 0 init finished in 30 msecs [DEBUG] PCI: 00:00:00.0 init [DEBUG] Assigning IRQ 10 to PCI: 00:00:01.3 [DEBUG] Assigning IRQ 11 to PCI: 00:00:03.0 [DEBUG] PCI: 00:00:00.0 init finished in 5 msecs [DEBUG] PCI: 00:00:01.0 init [DEBUG] RTC Init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x02 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [DEBUG] PCI: 00:00:01.0 init finished in 5 msecs [DEBUG] PCI: 00:00:01.1 init [DEBUG] IDE: Primary interface: on [DEBUG] IDE: Secondary interface: on [DEBUG] IDE: Access to legacy IDE ports: off [DEBUG] PCI: 00:00:01.1 init finished in 2 msecs [DEBUG] PCI: 00:00:02.0 init [DEBUG] PCI: 00:00:02.0 init finished in 35 msecs [DEBUG] PCI: 00:00:03.0 init [DEBUG] PCI: 00:00:03.0 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 57 / 36 ms [INFO ] Finalize devices... [INFO ] Devices finalized [INFO ] Timestamp - device setup done: 1012995431 [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms [INFO ] Timestamp - cbmem post: 1023365228 [DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 1 ms [INFO ] Timestamp - write tables: 1050553506 [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. [INFO ] Copying Interrupt Routing Table to 0x3fe92000... done. [DEBUG] PIRQ table: 128 bytes. [INFO ] QEMU: firmware config: Found 'etc/table-loader' [DEBUG] QEMU: found ACPI tables in fw_cfg. [INFO ] QEMU: firmware config: Found 'etc/acpi/rsdp' [DEBUG] QEMU: loading "etc/acpi/rsdp" to 0x3fe6e000 (len 20) [INFO ] QEMU: firmware config: Found 'etc/acpi/tables' [DEBUG] QEMU: loading "etc/acpi/tables" to 0x3fe6e040 (len 131072) [DEBUG] QEMU: loaded ACPI tables from fw_cfg. [DEBUG] Looking on 0x3fe6e000 for valid checksum [DEBUG] Checksum 1 passed [DEBUG] Checksum 2 passed all OK [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] ACPI: * SSDT [DEBUG] Found 2 CPU(s). [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] ACPI tables: 131136 bytes. [DEBUG] smbios_write_tables: 3fe66000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.22-671-g416cc665929e' [DEBUG] SMBIOS: Unknown CPU or CPU doesn't support Deterministic Cache CPUID leaf [INFO ] DOMAIN: 00000000 (QEMU Northbridge i440fx) [INFO ] QEMU: firmware config: Found 'etc/smbios/smbios-tables' [DEBUG] QEMU: found smbios tables in fw_cfg (len 327). [DEBUG] QEMU: coreboot type0 table found at 0x3fe66040. [DEBUG] QEMU: loading smbios tables to 0x3fe66086 [DEBUG] SMBIOS tables: 461 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8ff5 [DEBUG] Writing coreboot table at 0x3fe93000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-0000000000007fff: RAM [DEBUG] 2. 0000000000008000-000000000000dfff: RESERVED [DEBUG] 3. 000000000000e000-000000000009ffff: RAM [DEBUG] 4. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 5. 0000000000100000-000000003fe65fff: RAM [DEBUG] 6. 000000003fe66000-000000003fe9bfff: CONFIGURATION TABLES [DEBUG] 7. 000000003fe9c000-000000003ffccfff: RAMSTAGE [DEBUG] 8. 000000003ffcd000-000000003fffffff: CONFIGURATION TABLES [DEBUG] 9. 00000000fec00000-00000000fec00fff: RESERVED [DEBUG] 10. 00000000ff800000-00000000ffffffff: RESERVED [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [DEBUG] Wrote coreboot table at: 0x3fe93000, 0x310 bytes, checksum e5a4 [DEBUG] coreboot table: 808 bytes. [DEBUG] IMD ROOT 0. 0x3ffff000 0x00001000 [DEBUG] IMD SMALL 1. 0x3fffe000 0x00001000 [DEBUG] CONSOLE 2. 0x3ffde000 0x00020000 [DEBUG] TIME STAMP 3. 0x3ffdd000 0x00000910 [DEBUG] AFTER CAR 4. 0x3ffcd000 0x00010000 [DEBUG] RAMSTAGE 5. 0x3fe9b000 0x00132000 [DEBUG] COREBOOT 6. 0x3fe93000 0x00008000 [DEBUG] IRQ TABLE 7. 0x3fe92000 0x00001000 [DEBUG] ACPI 8. 0x3fe6e000 0x00024000 [DEBUG] SMBIOS 9. 0x3fe66000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x3fffec00 0x00000400 [DEBUG] RO MCACHE 1. 0x3fffe960 0x00000294 [DEBUG] FMAP 2. 0x3fffe8a0 0x000000b6 [DEBUG] ROMSTG STCK 3. 0x3fffe800 0x00000088 [INFO ] Timestamp - finalize chips: 1300590328 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 5 / 82 ms [INFO ] Timestamp - starting to load payload: 1308405624 [INFO ] CBFS: Found 'fallback/payload' @0x25480 size 0x10049 in mcache @0x3fffeb84 [DEBUG] Checking segment from ROM address 0xffc256ac [DEBUG] Checking segment from ROM address 0xffc256c8 [DEBUG] Loading segment from ROM address 0xffc256ac [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x00100000 memsize 0x135a30 srcaddr 0xffc256e4 filesize 0x10011 [DEBUG] Loading Segment: addr: 0x00100000 memsz: 0x0000000000135a30 filesz: 0x0000000000010011 [DEBUG] using LZMA [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 1342618898 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 1362402424 [DEBUG] Clearing Segment: addr: 0x000000000011eb68 memsz: 0x0000000000116ec8 [DEBUG] Loading segment from ROM address 0xffc256c8 [DEBUG] Entry Point 0x00100000 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 6 / 17 ms [DEBUG] Jumping to boot code at 0x00100000(0x3fe93000) [INFO ] Timestamp - selfboot jump: 1382362947 coreboot: 4.22-671-g416cc665929e FILO version 0.6.0 (pmenzel@abreu) Sun Feb 4 13:23:12 UTC 2024 Press <Enter> for default boot, or <Esc> for boot prompt... timed out boot: hda1:/vmlinuz initrd=hda1:/initrd.img root=/dev/sda1 ro quiet console=ttyS0,115200 ATA-0: [io ports 0x1f0-0x1f7,0x3f6] * hda [ATA Disk]: QEMU HARDDISK Found Linux version 5.6.0-1-686-pae (debian-kernel(a)lists.debian.org) #1 SMP Debian 5.6.7-1 (2020-04-29) relocatable bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... [ 0.051630] kernel BUG at arch/x86/kernel/apic/apic.c:1629! [ 0.052637] invalid opcode: 0000 [#1] SMP PTI [ 0.053267] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.6.0-1-686-pae #1 Debian 5.6.7-1 [ 0.054409] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 4.22-671-g416cc665929e 02/02/2024 [ 0.055811] EIP: setup_local_APIC+0x478/0x4b0 [ 0.056427] Code: fe ff ff 85 d2 0f 8f bd 11 00 00 a1 e0 06 93 c5 ba 00 07 01 00 8b 48 08 b8 50 03 00 00 e8 20 92 6f 00 e9 db fe ff ff 8d 76 00 <0f> 0b 8d b6 00 00 00 00 0f 0b e9 4b fc ff ff e8 d4 4b 02 00 a1 e0 [ 0.058843] EAX: 00000000 EBX: 00000000 ECX: 00000000 EDX: ffffffff [ 0.059700] ESI: c5aac8cd EDI: 00000000 EBP: c5993f64 ESP: c5993f14 [ 0.060676] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 [ 0.061610] CR0: 80050033 CR2: ff9ff000 CR3: 05b48000 CR4: 000006b0 [ 0.062494] Call Trace: [ 0.062876] ? vprintk_default+0x17/0x20 [ 0.063547] ? kvm_arch_para_features+0x43/0x80 [ 0.064399] apic_intr_mode_init+0xf4/0x10a [ 0.065197] x86_late_time_init+0x1d/0x24 [ 0.066421] start_kernel+0x3f9/0x4ac [ 0.066965] i386_start_kernel+0x48/0x4a [ 0.067506] startup_32_smp+0x164/0x168 [ 0.068167] Modules linked in: [ 0.068759] ---[ end trace 78220014fc8c5bde ]--- [ 0.069553] EIP: setup_local_APIC+0x478/0x4b0 [ 0.070297] Code: fe ff ff 85 d2 0f 8f bd 11 00 00 a1 e0 06 93 c5 ba 00 07 01 00 8b 48 08 b8 50 03 00 00 e8 20 92 6f 00 e9 db fe ff ff 8d 76 00 <0f> 0b 8d b6 00 00 00 00 0f 0b e9 4b fc ff ff e8 d4 4b 02 00 a1 e0 [ 0.073445] EAX: 00000000 EBX: 00000000 ECX: 00000000 EDX: ffffffff [ 0.074518] ESI: c5aac8cd EDI: 00000000 EBP: c5993f64 ESP: c5993f14 [ 0.075590] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 [ 0.076777] CR0: 80050033 CR2: ff9ff000 CR3: 05b48000 CR4: 000006b0 [ 0.077875] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.079101] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- ``` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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src/soc/intel/xeon_sp/Kconfig:95:warning: config symbol defined without type
by Mike Banon 18 Feb '24

18 Feb '24

After this commit - https://review.coreboot.org/c/coreboot/+/79058 - now I always have this warning while doing a "make menuconfig" : src/soc/intel/xeon_sp/Kconfig:95:warning: config symbol defined without type To fix this, please add the "bool" line before "default y" to specify the config symbol type. P.S. wrote about this problem under the change about ~1 month ago, but maybe the notifications are not working for the merged changes - so posting it here just in case -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 16 Feb '24

16 Feb '24

Dear community, Kindly note that the upcoming coreboot leadership meeting is scheduled for Wednesday, February 21, 2024. [1] Please take a moment to update the current agenda items with matters you wish to see addressed during the meeting. [2] [1](https://bbb.sfconservancy.org/b/mar-sfn-e22-axi). [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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Makefile classes-y vs subdirs-y
by Maximilian Brune 16 Feb '24

16 Feb '24

I am currently working a little bit on on makefile stuff and got a bit confused. Looking at the documentation it seems like `subdirs` is one of the possible `classes` that we have. But then I looked at payloads/libpayload/Makefile.mk file at this location: https://elixir.bootlin.com/coreboot/latest/source/payloads/libpayload/Makef… and it seems to add classes where I would have expected it to use subdirs-y instead. Can someone explain to me when to use classes-y and when to use subdirs-y?

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coreboot 24.02 release tag on next Monday!
by Felix Singer 13 Feb '24

13 Feb '24

The next coreboot release tag is scheduled for next Monday, February 19th! With the upcoming release we are changing our release number format from a version number to a date format. So it will be versioned 24.02. As always, please test any mainboards, give feedback, and if possible submit a patch for review if you found an issue. We appreciate any help. Also, let us know if there are any patches which need to make it into the release. You can do that by responding to this email and by adding the following hashtag to the related patch on Gerrit. The hashtag field is shown after clicking on the "show all" button from the top left information block of a patch. coreboot_release_2402 [1] We are using another hashtag in order to track patches which are important or useful in some way, maybe even ready to be submitted, but might break something and thus the risk is too high right before the release. So we prefer to submit them after the release which gives enough time for testing until the next release. Examples are version updates to the toolchain or updates to the FSP submodule pointer. The hashtag is as follows: coreboot_post_release_2402 [2] Please don't hesitate and reach out to us if you have any question. Felix --- [1] https://review.coreboot.org/q/hashtag:coreboot_release_2402 [2] https://review.coreboot.org/q/hashtag:coreboot_post_release_2402

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Termin mit Hinweis abgesagt: coreboot Leadership Meeting - Every 2 weeks from 11:00 to 12:00 on Wednesday (MST) (coreboot@coreboot.org)
by coreboot org 11 Feb '24

11 Feb '24

Dieser Termin wurde mit folgendem Hinweis abgesagt: "Updated with link to BigBlueButton meeting space." coreboot Leadership Meeting Every 2 weeks from 11:00 to 12:00 on Wednesday Mountain Time - Denver Standort US-BLD-PEARL2930-1-A-Nine-banded Armadillo (6) [GVC] https://www.google.com/maps/search/US-BLD-PEARL2930-1-A-Nine-banded+Armadil… Mit Google Meet teilnehmen https://meet.google.com/pyt-newq-rbb?hs=224 Per Telefon teilnehmen (US) +1 608-618-4744 PIN: 143813170 Weitere Telefonnummern https://tel.meet/pyt-newq-rbb?pin=6680344120895&hs=0 The meeting will be held via BigBlueButtonhttps://bbb.sfconservancy.org/b/mar-sfn-e22-axicoreboot leadership meeting minutesUse the number and pin below to join the meeting.United States (US): +1-718-247-9666PIN: 89421 Organisator pgeorgi(a)google.com pgeorgi(a)google.com ~~//~~ Einladung von Google Kalender: https://calendar.google.com/calendar/ Sie erhalten diese E-Mail, weil Sie ein Gast des Termins sind. Wenn Sie keine weiteren Informationen zu diesem Termin erhalten möchten, lehnen Sie die Einladung ab. Wenn Sie diese Einladung weiterleiten, kann jeder Empfänger eine Antwort an den Organisator senden und zur Gästeliste hinzugefügt werden. Außerdem könnte er weitere Nutzer einladen und Ihre Antwort ändern. Weitere Informationen https://support.google.com/calendar/answer/37135#forwarding

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[coreboot - Bug #522] (New) `region_overlap()` function might not work as expected due to an integer overflow in `region_end()` function.
by Vadim Zaliva 10 Feb '24

10 Feb '24

Issue #522 has been reported by Vadim Zaliva. ---------------------------------------- Bug #522: `region_overlap()` function might not work as expected due to an integer overflow in `region_end()` function. https://ticket.coreboot.org/issues/522 * Author: Vadim Zaliva * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-12-27 * Affected versions: master ---------------------------------------- `region_overlap()` function checks whether or not two memory regions overlap. Memory regions are represented as a region struct that contains the region's offset and size. This function then relies on `region_end()` function to compute the end of the region. `region_end()` function is susceptible to an integer overflow, which might result in the incorrect behaviour of `region_overlap()` function. An example of inputs that lead to wrong behaviour: ``` struct region r1 = {SIZE_MAX - 10, 20}; struct region r2 = {SIZE_MAX - 20, 15}; ``` It returns 0, but since the regions actually overlap, it should return 1. `region_overlap()` function is used in `smm_region_overlaps_handler()` function, which is itself used in SMI handlers to validate address values that come from an untrusted environment. This is necessary to prevent security vulnerabilities such as described in [BARing the System by Yuriy Bulygin, Oleksandr Bazhaniuk et al.](https://www.c7zero.info/stuff/REConBrussels2017_BARing_the_system.pdf) We do not have an example of an exploit based on this incorrect behaviour and are aware of the existence of one. However, theoretically, this could lead to security vulnerabilities. This bug was found during an ongoing [Coreboot Formal Verification Project](https://zaliva.org/UCSC-Twisted-Presentation-20231211.pdf), which aims to prove some important security properties of the coreboot’s SMI handler for the Gemini Lake/Octopus platform using Coq proof assistant and Verified Software Toolchain framework. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

6 16

2024-02-07 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 08 Feb '24

08 Feb '24

# 2024-02-07 - coreboot Leadership Meeting Minutes ## Attendees Mina Asante, Martin Roth, Felix Singer, Jay Talbott, Werner Zeh, Matt Devillier, Patrick Georgi, Ahmed Elgogary, Jonathan Hall, Felix Held, Nicholas Chin, Simon Glass, Julius Werner, Varshit Panda, David Hendricks, Nico Huber, Lean Sheng Tan, Max Brune. ## Open Action Items * 2024-01-10 * [Open] Werner: Push patch based on https://ticket.coreboot.org/issues/522 * Nico: https://review.coreboot.org/q/topic:enforce_region_api * [Open] Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. * 2023-11-01 * [Started]Martin: Shallow submodules - document & test, then update submodules if testing goes well. Additionally look at whether the .branch option helps. * We can save over 900MB by using shallow submodules. * [Projects & RFCs](https://docs.google.com/document/d/15H2m4swdESSgGaIuINOePkyst8b39Y7Lu…. * Making progress - see email thread. * 2023-10-4 * Martin: Write a tutorial for gerrit - Feel free to help. [Started](https://docs.google.com/document/d/1Z8igNdgBG5_Qlr4kKRtlbpKaZo9RUg…. * [Open] OSFF: Look into making a video about using gerrit. * Discussed with Christian who felt this was a good plan. * Look at next year. * [Open] Martin: Write a document about vendorcode submodules. ## Minutes ### [Martin/Felix] Switching to BigBlueButton. * The upcoming meeting in two weeks (02/21/24) will take place on BigBlueButton instead of Google Chat. Further information will be published to the mailing list between Wednesday's meeting and the following one. * New meeting link to join the leadership meeting: * https://bbb.sfconservancy.org/b/mar-sfn-e22-axi * For phone access, call +1-718-247-9666, then enter 89421 as the conference PIN number. * It looks like there’s only a USA phone number. ### [FelixS] Building a community FSP for Intel based platforms * Initial coreboot support for Intel consumer platforms mostly comes with Google Chromebooks. * coreboot support for a wide range of mainboards is only possible if Intel releases FSP binaries. For some platforms Intel refuses to release a FSP binary and Intel also refuses to fix issues within FSP. * How to make coreboot more independent? People have tried convincing Intel to make FSP open source. It seems unlikely that anything in that regard happens any time soon. * As a compromise, I am proposing to build our own FSP from scratch that is built by the community, specifically companies. It's still meant to be closed-source, since Intel won't allow us to write open source code, but then we are able to extend and improve it whenever we want. * Will Intel allow us to distribute our own binaries if the code is completely written by ourselves? * Possible issues * Getting a multi-party NDA * [Werner] First of all we need an entity which could be the NDA partner (OSFF could probably be?) * Getting a license so that we are allowed to distribute it * [Werner]The license that comes with the FSP code that I am aware of explicitly inhibits code changes and productive use of self-built binaries. How would we ensure this? * [FelixS] AFAIK the standard license allows us to do code changes but it doesn’t allow us distributing the binary over let’s say a website. So I am wondering if it’s different with something we build ourselves. * [Sheng] Do you have connections with Intel folks to make this happen or initiate the discussion? Is there a solid plan for this, to outline the goals, process, and details with Intel? Or is this just a mere suggestion that is probably not very practical? Since this is not an Intel specific issue, how about AMD? This won't happen overnight - who is going to lead this initiative with Silicon vendors, initiate discussions and meetings (and it will be a difficult and consuming process), collect feedback from all parties, and craft out a solid plan to move ahead? * [Martin] In coreboot’s agreement with SFC, we agreed that any and all software and/or documentation developed and maintained by the Project and the Project’s participants will be distributed solely as Free Software. * Because of this agreement, while this proposed FSP could be interesting to the coreboot group, it’s not, and cannot be, a coreboot project. Since we wouldn’t be able to open source the proposed FSP, I’m not even convinced that it’s something that should be discussed in this meeting. * [Felix S.] Just wants to hear the opinion of the coreboot community and not try to add this project to coreboot’s projects * [Jonathan H] It would be hard to get manager support since it’s not open source. * [Jay T] A separate license is required for release. The FSP needs to be identified as non-intel. * [Nico] We can focus on FSP-S and publish everything that doesn’t have to be secret as open source. What does intel feel about this? * [Martin]: if we’re doing it as open source, why do it as FSP, why not just do it as coreboot? * David: Look at getting a consortium of companies to sit down with intel and try to work with them to make FSP better. This can’t be done privately, cutting intel out of the loop. * Werner: OSFF is ready to take over things like this instead of doing it as a consortium. Intel has typically even rejected the idea of joining the OSFF to do something like this. * David: Start with contacting intel. I can put Felix in touch with someone from intel. * Sheng: Try building on top of Subrata’s success: 75% of FSPS is getting moved to the platform firmware. * https://blog.osfw.foundation/breaking-the-boundary-a-way-to-create-your-own… * Incorporate Fiano tool as part of Intel coreboot build process to remove the unused FSP modules during build time. That will help to shrink the FSP-S binary by 75%. For the rest of the 25%, the community can start poking around it by trying to implement those as part of native coreboot code. * Resume the work on LibGFXinit. If LibGfx driver is production ready, then we could further shrink FSP-S by removing the graphic init module from it. ### [Arthur] Status update on ARM LBBR bootflow (was asked last meeting) * Nothing to discuss so not sure if this needs to be on the agenda. * Things are progressing along with the LBBR Engineering Change Request to include other bootflow recommendations where coreboot is BL1 * It’s an industry wide spec, so a wide range of partners were asked for input, which takes time * [Martin] We were told in a previous leadership meeting back in October or November that the decision of what to include in the spec would be made at a meeting in January, which is why we pushed so hard to get the decision about the ARM coreboot solutions to be wrapped up. * As far as it being on the agenda, I think even letting us know that things are just progressing but not resolved yet is information that should be shared instead of just leaving people wondering what’s going on. * When should we expect an actual update? June? December? 2025? * [Sheng] No idea..you know how big corporate’s meetings go.. People in the meeting keep asking more questions. As ARM has a wide range of ecosystem partners, and they want to be heard. We are also wondering and equally frustrated, but nothing within 9elements control, we already did our best as possible and keep putting in more resources to help resolve the questions from Arm partners.. Just want to be very cautious here that we did not promise fast approval, but the CB decision was crucial to kickstart the discussion and help to accelerate the process. Hopefully ARM SystemReady will finalize the decision in the coming months. Will share more when we have updates. * When are the patches in question expecting to be merged? * [Sheng] As per I got the confirmation and agreement from leadership in the meeting that with the conditional approval, the patches will be merged immediately after we got confirmation from ARM that the proposed coreboot->TFA is included in the LBBR spec. If the condition changes then will need to bring it up again. ### [Elyes] revert & get rid of write{8,16,32,64}p (readXXp? ). * See Julius’s comment here : https://review.coreboot.org/c/coreboot/+/80193. * Julius: There’s a reason we use void pointers - we want to practice good hygiene and use the correct types for variables. * FelixH: In some cases you have #defines for different MMIO addresses. You need additional typecasts in the code for this. * Werner: Adding the typecast indicates that the developer is doing this intentionally. * David: Something in linux coding guidelines about not hiding pointers as typedefs. This is in the same vein. * Felix & Nico - Agree that removing these will make the code more cluttered. * MaxB: No reason to have these functions - It just hides the typecast. So what if it adds just a bit of clutter. * David: I’d stick with the older format. * Werner: I’m with David - just cast the variable properly. * David: This could also create a bad precedent. * David: Fix the variables that are being passed in rather than casting them? * We’d like one implementation instead of two. Let’s make a decision about what we want to use. * Let’s figure out where the variables are created and see why they’re created with an incorrect type. * FelixH: Get stats of the usage of the different function types. Suspects that most values are actually uintptr_t. ### [Martin] coreboot 24.02 release in just under 2 weeks * Release planned for February 19, 2024. ### [SimonG] Coreboot Control Block again * [Link](https://review.coreboot.org/c/coreboot/+/77712). * Julius doesn’t feel that the benefit is not worth the maintenance cost. * CBFS is the main alternative. CCB should either have its own file or use one of the existing * Wener Zeh, Matt Deviller and David Hendricks generally approve to get this feature in. # Next meeting * February 21, 2024. * [Meeting link](https://bbb.sfconservancy.org/b/mar-sfn-e22-axi). * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes * [2024-02-07](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1….

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