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答复: High-End Desktop Support
by YhLu 13 Jun '03

13 Jun '03

Ron, Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA support. Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年6月12日 8:37 收件人: Peter Fedorow 抄送: linuxbios(a)clustermatic.org 主题: Re: High-End Desktop Support On Thu, 12 Jun 2003, Peter Fedorow wrote: > I'm looking for a fully supported motherboard that can accept at least a > 2 GHz Pentium 4 or AMD Athlon. intel e7500, 7501, etc. are supported. ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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答复: High-End Desktop Support
by YhLu 13 Jun '03

13 Jun '03

Eric, I am working on porting linuxbios to Tyan s2725. The southbridge is ICH5. I have copied 82801ca to 82801er. And update pci_ids.h to add some ICH5 device id. I compare the Intel whitepaper, only need to comment out several line in ich5_ioapi.c. because ICH5 has no operation to index 3 reg. I didn't initialize USB and Serial ATA. I used e1000.ebi from Etherboot 5.0.8. I only got the following result. The ebi size is 18164, so I set ROM_IMAGE_SIZE to 46*1024. I wonder why the size if not right: 0x4564 = 17764. But the EBI is 18164. Regards Yinghai Lu Console output: Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xffff0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564 (cleaned up) New segment addr 0x94000 size 0x7168 offset 0x60 filesize 0x4564 Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000007168 filesz: 0x00 00000000004564 Clearing Segment: addr: 0x0000000000098564 memsz: 0x0000000000002c04 Jumping to boot code at 0x�� -----�ʼ�ԭ��----- ��: YhLu ��ʱ��: 2003��6��12�� 17:12 �ռ��: ron minnich; Peter Fedorow ��: linuxbios(a)clustermatic.org ��: ��: High-End Desktop Support Ron, Any plan to make it support ICH5. It has USB 2.0 support and Serial ATA support. Yinghai Lu -----�ʼ�ԭ��----- ��: ron minnich [mailto:rminnich@lanl.gov] ��ʱ��: 2003��6��12�� 8:37 �ռ��: Peter Fedorow ��: linuxbios(a)clustermatic.org ��: Re: High-End Desktop Support On Thu, 12 Jun 2003, Peter Fedorow wrote: > I'm looking for a fully supported motherboard that can accept at least a > 2 GHz Pentium 4 or AMD Athlon. intel e7500, 7501, etc. are supported. ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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High-End Desktop Support
by Peter Fedorow 12 Jun '03

12 Jun '03

I hope this is an appropriate question to ask here. Does LinuxBIOS support any of the current high-end desktop chipsets? I checked the LinuxBIOS status page, but I didn't see any matches. I'm looking for a fully supported motherboard that can accept at least a 2 GHz Pentium 4 or AMD Athlon. Peter

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config language
by ron minnich 11 Jun '03

11 Jun '03

Eric has pointed out to me that we need a tree to properly describe the new complex systems such as K8. The current config language is not sufficient to do the job. I've been thinking about mods to the language that preserve the current simplicity for the vast majority of motherboards out there, while at the same time allowing a complex hierarchy to be described. I think I have an idea. Currently we say things like this: southbridge vendor/model ... superio vendor/model ... This syntax is actually sufficient for something like 95% of the motherboards we need to support. But what if we have southbridge vendor/model ... southbridge vendor/model ... superio vendor/model ... which southbridge is the superio on? Here is my proposed change southbridge vendor/model[=<tag>] [parent=<tag>] ... superio vendor/model[=<tag>] [parent=<tag>] ... (note this syntax applies to all the types of parts) Consider the simple case. The one southbridge is given a default tag of southbridge, with the default parent of northbridge. The superio is given the default tag of superio, with the default parent of southbridge. It all works. Consider the hard case. southbridge intel/xyz=sb1 ... southbridge intel/xyz=sb2 ... superio NSC/abs parent=sb1 ... If there is more than one northbridge, then we can set the parent tag for the southbridge. This syntax allows arbitrary trees to be described; it is as simple in the base case as the current one; and it should be fairly straightforward to implement. Computing the path to a given part is then easy. Some flexibility in the tags should be possible. The tag could allude to an actual tag, or a part type (southbridge), or a part vendor/manufacturer pair (intel/xyz). As long as the tag specifies something unique, it should be acceptable. Another way to do it is this: southbridge [tag=<tag>] [parent=<tag>] any preference for syntax? Comments? ron

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linuxbios and bochs
by Brian G. Rhodes 11 Jun '03

11 Jun '03

I'm booting linuxbios with a adlo/bochs payload on a VIA EPIA 800. I have also disabled vga in bochs so thatit does not hang when vgabios is not present. Bochs will load about 10% of the time when rebooting the system. The rest of the time it will hang. I am quite certain that it is somewhere in bochs where the problem exists since I can load etherboot from linuxbios without issue. The times bochs does load from linux generally hangs shortly after lilo loads the kernel. What I am wondering is if anyone else has had this problem and come up with a workaround, or knows the reason, or atleast where I should look more closely. Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 POST: 0xf8 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 (cleaned up) New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 Loading Segment: addr: 0x00000000077649d8 memsz: 0x0000000000020400 filesz: 0x00000 Jumping to boot code at 0x7c00 POST: 0xfe Brian G Rhodes bgr(a)linespeed.net brhodes(a)visualcircuits.com +1 612-741-1191

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Re: doc ipl image
by roger 11 Jun '03

11 Jun '03

ok. docipl /path/to/src/mainboard/asus/cua/ipl.S and Python configure made the Makefiles, however dd fails with a negative number with "docipl" in the config file. So i'm doing this seperately and copying the created dociple to another folder and then re-running the configure/make without the "docipl" option to build the linuxbios.image and linuxkernel.image images. I'm rebuilding the kernel again for the DoC (looks like it might be wise to build mtd/mtdchar/doc2001 modules into the kernel) and am working on a serial console for remote console. So far, i've gotten nothing to boot. Just the same scenario as a box without a bios chip. Although, I could have sworn i had some additional hdd activity on the last attempt. One additional question, if HAVE_FRAMEBUFFER=0, there still is console activity on the monitor right? (-i think i'm interpretting this correctly-). wew! ain't google grand?!? one can actually have a one-way conversion with himself via email!!! On Tue, 2003-06-10 at 22:24, roger wrote: > Just a quick follow-up. I noticed that I had to add the following line > in the config file: > > docipl /pathto/ipl.S > > ok. now for ipl.S (for a 440BX chipset?) -- Roger http://www.eskimo.com/~roger/index.html

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doc ipl image
by roger 10 Jun '03

10 Jun '03

ok. wew. searched, read, reboots (did this in a loop for 10x's). i've gotten p5 images built and have been able to recognize and write to the DoC (many thanx to a kernel oops w/ devbios project and it's apperant incompatability with apm). After erasing the DoC, I'm realizing that I need an ipl image burned prior to burning linuxbios.image & linuxkernel.image images to the rom. Ipl is needed to boot linuxbios. Linuxbios is needed to boot linuxkernel. (And so on...) I see that the ipl.asm is provided only by m-sys on a NDA. (btw, using an Intel 440bx chipset here). -- Roger http://www.eskimo.com/~roger/index.html

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romcc progress.
by ebiederman＠lnxi.com 10 Jun '03

10 Jun '03

I have just implemented inline assembly and a better allocator in romcc. It will now use sse and mmx registers when you give it the appropriate -mcpu= option. I am not happy with the command line options but fixing them is easy. In addition the quality of the register allocations has improved to the point that it looks quite a bit like it was done by hand. There are limits but there are fewer stupid things happening. The inline assembly is syntactically the same as gcc's. But it is not 100% compatible with gcc. The goal is to be as compatible with gcc as gcc is compatible with gcc between ports. In practice this means that romcc supports a subset of what gcc does on x86, with respect to constraints. On inline assembly versus builtin operations. A compiler has a lot more potential to optimize code in a builtin so I will continue to implement builtins. Support wise inline assembly with parameters is a pain to initially implement but there really is not a support burden after that. And there are some operations where there is not gain making them a builtin. The code is now checked into the freebios2 tree. And I can get back to exercising romcc by writing code with it. Eric

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答复: 答复: 答复: new config language.
by YhLu 09 Jun '03

09 Jun '03

I changeg the stack size from 0x2000 to 0x10000, and the result is that it retrys more times. I have got 1.5G memory installed and I found the code in ramtest only hard code that to 512M, is cause the problem? LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting... Bootstrap cpu setting up coherent ht domain.... done. PCI: 00:01.00 PCI: 00:01.01 PCI: 00:02.00 PCI: 00:02.01 PCI: 00:03.00 PCI: 00:04.00 PCI: 00:04.01 PCI: 00:04.02 PCI: 00:04.03 PCI: 00:04.05 PCI: 00:04.06 PCI: 00:18.00 PCI: 00:18.01 PCI: 00:18.02 PCI: 00:18.03 SMBus controller enabled Ram1 setting up CPU0 northbridge registers done. Ram2 Ram3 dcl: 080c8000 Initializing memory: done Ram4 Ram5 Ram6 dimm: 50 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 5080 dimm: 5180 dimm: 5280 dimm: 5380 DRAM fill: 00000000-00001000 00001000 DRAM filled DRAM verify: 00000000-00001000 00001000 DRAM verified Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting... LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting... Bootstrap cpu CPU INIT Detected. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting... LinuxBIOS-1.1.02.0Fallback Mon Jun 9 23:14:16 PDT 2003 starting... Bootstrap cpu CPU INIT Detected. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. So I would find one AMD to verify the code. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年6月9日 22:36 收件人: YhLu 抄送: ron minnich; linuxbios(a)clustermatic.org 主题: Re: 答复: 答复: new config language. YhLu <YhLu(a)tyan.com> writes: > Ron, > > Is there any MB can boot to execute into LinuxBIOS after copying it to RAM? > > The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8 is > 0x4000. How should I set the value to make the LinuxBIOS can boot into > hardwaremain.c. > It seems MB only execute the auto.c and crt0.base and can not jump to the > right address. ??????????????? I think there is a fundamental disconnect here. Except when I miscompile auto.c the AMD reference board boots fine. And in this aspect the code is fundamentally the same as earlier revision of LinuxBIOS. auto.c just gets compiles into auto.inc And I can't think of a board where I have had problems with jumping to hardwaremain. _RAMBASE should not strongly affect anything, it just need to be in a location where the ram initialization code always puts ram. Only with respect to stack size, and the LinuxBIOS tables should it have any issues with various locations in ram. Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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答复: 答复: new config language.
by YhLu 09 Jun '03

09 Jun '03

Ron, Is there any MB can boot to execute into LinuxBIOS after copying it to RAM? The _RAMBASE WE use for E7501 is 0x8000, and the FreeBIOS2 default for K8 is 0x4000. How should I set the value to make the LinuxBIOS can boot into hardwaremain.c. It seems MB only execute the auto.c and crt0.base and can not jump to the right address. Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年6月9日 22:01 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: Re: 答复: new config language. On Mon, 9 Jun 2003, YhLu wrote: > How about the status of freebios2 support on K8? we're working on it. There are 3 big efforts going on. First, Eric is working on romcc for K8 so that it works well. Suse is trying to get it to boot. I am working on a new config language which I hope is rich enough to capture the needs of freebios2. Where are we? We are all collectively close. But we're not done. ron

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