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Newbie questions: Linuxbios on Geode GX1
by Joep Jansen 20 May '03

20 May '03

Hi, I am new to this list, and I have a couple of questions. I have an embedded CPU module (Kontron ETX-MGX with a Geode GX1), and I am looking into the possibility of putting linuxbios on it. The board contains: * a Geode GX1 CPU * CS5530A I/O companion south bridge * 64 MB RAM * AM29F040B 512 KB flash ROM with Phoenix BIOS * Compact Flash slot on IDE1 master The flash chip is soldered on the board, so replacing the BIOS chip is no option. My main question is: How can I safely flash a new BIOS? I have a BIOS ROM image file, and the Phoenix Phlash utility which allows to restore and update the BIOS. I understand the flash has a boot block which is able to restore a corrupted BIOS. I don't know whether the boot block is protected from erasing and / or reprogramming. I do know that it needs a specialy wired "key" in the serial port to enable reprogramming. My idea would be to use this utility to put linuxbios in the flash ROM. I would leave the boot block in place so that I am able to restore the original BIOS if things go wrong, or to put in a new version of linuxbios. Does anyone have experience with this? What would I need to do to convince Phlash to flash the linuxbios? Do I need to make changes to linuxbios to accomodate this scheme? Another question: How do I configure linuxbios to boot a linux kernel from the Compact Flash card? Do I need a specific "payload" program in addition to linuxbios? Any help is greatly appreciated! Joep Jansen -- Frog Navigation Systems B.V. mail to: joep(a)frog.nl Krommewetering 21 URL: http://www.frog.nl 3543AP UTRECHT Tel: (+31) 30 2 440 550 Nederland / the Netherlands Fax: (+31) 30 2 440 700

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Re: config language and 2.0
by jarcher＠pobox.com 20 May '03

20 May '03

Yeah, I agree it's hard to not go too far. But coming from a compiler company you begin to look at everything as a language. Honestly, having gone through my first port/debug this weekend, I would say another feature would be a index listing file of the include files, paths, and the generated options would be nice. I spent a lot of time figuring out just which include file was being used. A second point is on items for 2.0. I had to track down three places where the serial port got its baud rate reset. I kept loosing debug messages. How about some flags to test if a device is already initialized? Jordan At 07:54 AM 5/20/2003 -0600, ron minnich wrote: >On Tue, 20 May 2003 jarcher(a)pobox.com wrote: > > > I may be going to far here, but what about the ability to define new > > devices? Or composite devices. > > > > define warpdisk > > cpu p3 # Warp disk controller > > include vendor/warpdisk_driver.inc > > end > > > > mainboard vendor/model > > cpu p5 > > warpdisk > > ...config... > > end > > > > Also I don't know if the current structure allows options. > > > > superio vendor/model IDE2=0 # For setting #defines for this > > included device. > > warpdisk ID=0 MAXDISK=3 > > warpdisk ID=1 MAXDISK=2 > > > > Jordan > >well, at what point are we going overboard? but we'll look at it. It's an >interesting idea. > >There was a reason I made the original language so dumb ... :=) Once you >make it a real language too many things are possible :-) > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios

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Re: config language
by jarcher＠pobox.com 20 May '03

20 May '03

I may be going to far here, but what about the ability to define new devices? Or composite devices. define warpdisk cpu p3 # Warp disk controller include vendor/warpdisk_driver.inc end mainboard vendor/model cpu p5 warpdisk ...config... end Also I don't know if the current structure allows options. superio vendor/model IDE2=0 # For setting #defines for this included device. warpdisk ID=0 MAXDISK=3 warpdisk ID=1 MAXDISK=2 Jordan >On Mon, 19 May 2003, Greg Watson wrote: > > > Defining the tree from bottom-up is somewhat non-intuitive and > > potentially confusing. It seems more natural to define the tree > > structure top-down as follows: > > > > mainboard vendor/model > > cpu p5 > > southbridge vendor/model > > end > > southbridge vendor/model2 > > superio vendor/model > > ...config... > > end > > end > > end > >OH, ok, you win. I had thought of this but hate the idea of writing a >parser ... string handling in C is like walking on broken glass. > > > > mainboard motorola/sandpoint > > pmc altimus/mpc7500 > > northbridge motorola/mpc107 > > end > > southbridge windbond/w83c553 > > superio NSC/pc97307 > > com1={1} > > com2={1} > > floppy=0 > > lpt=1 > > keyboard=1 > > hwmonitor=1 > > end > > end > > nvram > > flash > > end > >agreed, it's pretty. But NOBODY is allowed to suggest lexical scoping from >indentation. That's not allowed :-) > >Greg, parser in the usual lex/yacc/C mode or .... I'll see if anybody's >got parsers written in python. > >ron

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new config tool
by ron minnich 20 May '03

20 May '03

I'm looking at a parser generator called YAPPS, more when I know how it will go. ron

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Re: [PATCH] Automatic RAM detection for VT8601
by NEWBELL7＠magicn.com 20 May '03

20 May '03

Hi !!!! I have a question about ADLO. My LinuxBIOS + etherboot + ADLO go through to ADLO, but stop at " sti " instruction before jumping to Bochs BIOS. I look up "sti" from Intel IA32 Instruction set Volume 2. I read that "sti" is "protected mode virtual interrupt enable". I removed "sti" from ADLO because it is real mode. Does It affect badly to my EPIA operation ? ps.> If I reset my system with LinuxBIOS after booting it with PC BIOS, it works great. As result , What makes it works ? Need your help... Thanks. regards newbie

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Flashing Intel (L440GX) BIOS
by Jonathan B. Horen 20 May '03

20 May '03

Shalom! With lots of assistance from Ron Minnich, I've been able to patch a 2.4.20 kernel with the LinuxBIOS extensions and successfully compile and boot from it. I've also succeeded in compiling a romimage for the Intel L440GX. I've downloaded Intel's latest System Update Package -- lsup2_0.exe -- for the L440GX motherboard. My question is about what to do with what I've now got. That is, how do I get this romimage onto my motherboard(s)? Running lsup2_0.exe on a Windows system gives me, among other things, a BIOS directory. This directory contains BAT files, README and RELNOTES, BIOS files, and their IFLASH.EXE utility. The 1.BAT file invokes: IFLASH.EXE /P P14-0133.BIO /R in which I assume /P gives the file to load (or the first file in a group of files to load), and /R reboots afterward... or not ;-) Since I don't want to install Intel's newer BIOS, but do want to install the LinuxBIOS I compiled, what do I do, from here? Any pointers to previous threads about flashing L440GX BIOS? -- JONATHAN B. HOREN UNIX SYSTEMS ADMINISTRATOR E: horen(a)mail.iucc.ac.il Inter-University Computation Center T: +972-(0)3-640-5203 Tel-Aviv University F: +972-(0)3-640-9118 Ramat-Aviv 69978 Israel

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Re: Reverse engineering
by Karl Hammar 20 May '03

20 May '03

> Is it legal to disassemble the proprietary VGA BIOS to learn how to > enable a particular VGA chip? > Of course, he (who?) will not copy any bits from the copyrighted code, > he'll just pick up register addresses and values, and its order. > If he would eventually write a code to enable VGA this way, > can we share the resulting code? > > -- > Takeshi A FreeBSD developer said that in the EU there is a law that says that you have the right to get the interface specifications. I don't know if he was right or wrong. Even if he is right, there could be conditions that makes it out of the reach anyhow. Regards, /Karl ----------------------------------------------------------------------- Karl Hammar Aspö Data karl(a)kalle.csb.ki.se Lilla Aspö 2340 Networks S-742 94 Östhammar +46 173 140 57 Computers Sweden +46 70 511 97 84 Consulting -----------------------------------------------------------------------

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RE: [PATCH] Automatic RAM detection for VT8601
by hcyun＠etri.re.kr 20 May '03

20 May '03

As for reset, you may can do it by asserting "Software PCI reset" on configuration space of PCI-to-ISA bridge. Heechul > -----Original Message----- > From: SONE Takeshi [mailto:ts1@cma.co.jp] > Sent: Tuesday, May 20, 2003 5:29 PM > To: NEWBELL7(a)magicn.com > Cc: linuxbios(a)clustermatic.org > Subject: Re: [PATCH] Automatic RAM detection for VT8601 > > > On Tue, May 20, 2003 at 02:15:23PM +0900, NEWBELL7(a)magicn.com wrote: > > I have a question about ADLO. My LinuxBIOS + etherboot + > ADLO go through > > to ADLO, but stop at " sti " instruction before jumping to > Bochs BIOS. > > I look up "sti" from Intel IA32 Instruction set Volume 2. > I read that > > "sti" is "protected mode virtual interrupt enable". > > > > I removed "sti" from ADLO because it is real mode. > > Does It affect badly to my EPIA operation ? > > sti should also work in real mode. > > > ps.> If I reset my system with LinuxBIOS after booting it > with PC BIOS, > > it works great. > > Linux's reboot code sometimes doesn't work for some reason. > (I think it resets only CPU) > > I wrote a small program to directly hit the power management device > found in EPIA to reset the system, not only CPU. > It works for me. > Changing 0x29 to 0x28 makes it power off instead of reboot. > See southbridge manual for detail. (0x4000 is PM base) > -- > Takeshi > > > > #include <sys/io.h> > > main() > { > iopl(3); > outb(0xff, 0x4001); > printf("01=%x\n", inb(0x4001)); > outb(0x20, 0x4005); > printf("05=%x\n", inb(0x4005)); > outw(0xff, 0x4020); > printf("20=%x\n", inw(0x4020)); > outb(0x29, 0x4005); > // while ((inb(0x4001) & 1) == 0) > // sleep(2); > } > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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[PATCH] Automatic RAM detection for VT8601
by SONE Takeshi 19 May '03

19 May '03

Hi, This patch adds automatic detection of installed RAM presence, size, and MA mapping type for VIA VT8601 northbridge. I tested this with VIA EPIA 5000 and 3 different type DIMMs. A. 64MB single sided (borrowed from my server :) B. 256MB double sided (borrowed from my desktop :) C. 256MB single sided (bought for EPIA) Timing was set to PC100 CL=3. (it's configurable at build time) EPIA has 2 DIMM slots, and 'empty' is possible in addition to 3 DIMMs, so there are 12 (=4*3) possible installation patterns. All patterns are tested with memtest86 3.0 as payload, to at least Test #2, and no error was found. Additionally DIMM B+C (512MB total) with PC133 CL=2 configuration was tested and all tests of memtest86's Std Test found no error. -- Takeshi

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PIRQ problem (Please try using pci=biosirq)
by dkotian3＠vsnl.net 19 May '03

19 May '03

Hi, I am using 256kb BIOS flashrom, etherboot, and kernel image on compact flash IDE . I get this error in LinuxBIOS. ***Extract*** Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...failed Wrote linuxbios table at: 00000500 - 0000064c checksum b79a ***Extract*** When I try do read from 0xf0000 after copying, it does shows 0xff instead some value. I had forced the sizeram to return 1MB less then the actual Ramsize to make it work with etherboot. When the kernel boots up, the ethernet interface does not come up. **Extract for the Linux kernel messaage** eth0: RealTek RTL8139 Fast Ethernet at 0xc4800000, 00:30:02:09:02:93, IRQ 0 PCI: No IRQ known for interrupt pin A of device 01:05.0. Please try using pci=biosirq. eth1: RealTek RTL8139 Fast Ethernet at 0xc4802000, 00:30:02:09:02:92, IRQ 0 **Extract for the Linux kernel messaage** I have tried the checkpir,etc on the irq tables. It is OK at the command prompt. But I still get this error. Any suggestion on this. Regards Deepak Regards Deepak

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