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I just updated the web page at www.linuxbios.org
by ron minnich 24 Jun '03

24 Jun '03

look at any STATUS you might own and see if it is right. Sorry for the delay. ron

2 1

Re: new config language.
by YhLu 24 Jun '03

24 Jun '03

Eric, Thanks for the info about ROMCC. The code about mem init in northbridge/amd/amdk8/coherent_ht.c and northbridge/amd/amdk8/raminit.c had some overlap. On bus 0, dev 0x18 and f 1. I will add something at northbridge/amd/amdk8/coherent_ht.c regards Yinghai Lu -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年6月20日 13:08 收件人: YhLu 抄送: ron minnich; linuxbios(a)clustermatic.org 主题: Re: new config language. YhLu <YhLu(a)tyan.com> writes: > Eric, > > Thanks for the advice. > I will try to add the SMP support in the northbridge/amd/amdk8 at first. OK. There are few levels of this. Coherent Hypertransport setup. Mapping resources to their location in the coherent HT domain. Memory Initialization on secondary cpus. Starting up the secondary cpus. Stefan Reinauer is currently working on Coherent Hypertransport initialization. And there is a hardcoded version of it in northbridge/amd/amdk8/coherent_ht. c Ron is currently working on getting the new Config language going and probably in the week or two we will switch over to that. While not writing memory initialization code I am busily getting the kinks out of romcc. I think I have just squashed the last of the bugs in register allocator. I thought I was there earlier but a few extra ones cropped up after I rewrote the algorithms so they ran in a reasonable amount of time. And since the reasons for my original hesitation are no longer valid I have implemented goto support in romcc. I think I am only short enumeration constants, macros with arguments, and switch statements to have a full implementation of C. Admittedly there are some things I cannot support like non const static variables. And I still have to fix the limits on variables, currently I don't limit chars and shorts when stored in larger integers to just the low bits of the register. Eric

4 22

Re: 答复: coherent hypertransport enumeration on opteron
by ron minnich 24 Jun '03

24 Jun '03

On 24 Jun 2003, Eric W. Biederman wrote: > Yes. It has been in the repository in src/include/device/pci_def.h > for a month now. At least according to CVS. gag. It came down to my machine here at work and not my x24. OK, more fun. ron

1 0

答复: coherent hypertransport enumeration on opteron
by YhLu 24 Jun '03

24 Jun '03

Stefan, I swap the PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000070, //1C The 4th line. It can go through setup_coherent_ht_domain. But seems then both CPU all works. Please refer the attached. Any problem. Regards Yinghai Lu LinuxBIOS-1.1.02.0Fallback Mon Jun 23 21:39:13 EDT 2003 starting... Bootstrap cpu setting up coherent ht domain.... done. P LinuxBIOS-1.1.02.0Fallback Mon Jun 23 21:39:13 EDT 2003 starting... I :L i0n0u:x0B1.I0O0S- 1.P1C.I0:2 .000F:a0l1.l0b1ac k MoPnC IJ:u n0 02:30 2.2010:3 9:P1C3I :E D0T0 :2002.0031 s :artPCinIg:. .0.0 03Copying LinuxBIOS to ram. .00 PCI: 00:04

3 4

Re: hidden IC2 bus on ASUS
by ebiederman＠lnxi.com 24 Jun '03

24 Jun '03

I am bouncing this to the LinuxBIOS list because most of the discusion happens there. And I am extremely busy at the moment. Rudolf Marek <MAREKR2(a)cs.felk.cvut.cz> writes: > Hello, > > I have ASUS A7S333 (Sis745). > > On I2C I got only one winbond chip and one unknown device. > No SPD eeprom no PLL. > > I read somewhere that you are curios to know if other ASUS mainboards > got this feature. So here is my answer. > > I want to enable the SPD i2c in case I can read the SPD timings. > (I wrote i2c driver patch for my 745 into lm_sensors, ten to my surprise > theese SPD and PLL devices "missing") > > Unfortunatelly I dont have SiS745 spec so I dont know where to trigger > this back. Would you give me some hint please? The only hint I have is that boards like this tend to have a mux on the i2c line. Either controlled by a gpio line. Or I have seen the controlled by an i2c device. > Thank you. > > Rudolf Marek > > CTU prague student. Welcome, Eric

1 0

Re: coherent hypertransport enumeration on opteron
by YhLu 24 Jun '03

24 Jun '03

I remember there is one type error on arch/i386/lib/pci_ops.c. Change one *val --> value How about your new build script progress? Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年6月23日 15:06 收件人: YhLu 抄送: Stefan Reinauer; ebiederman(a)lnxi.com; linuxbios(a)clustermatic.org 主题: Re: 答复: coherent hypertransport enumeration on opteron what is pci_def.h BTW? I can't build now. ron

3 2

答复: coherent hypertransport enumeration on opteron
by YhLu 24 Jun '03

24 Jun '03

Eric, After update raminit.c now MB can boot into linuxbios. The s2880 has six memory slot: 4 for CPU0 ,and 2 for CPU 1. I can only init 4 for CPU0. I have tried: #cp raminit.c raminit1.c and rename all function in the raminit1.c to xxxxx_1 copy genric_sdram.c to generic_sdram1.c in the sdram dir. Also add the calling function in auto1.c. and can not pass the test. Any advice on init RAM on second cpu northbridge? I have try to enable SMP support in LinuxBIOS and can not compile it through. Miss severl function. (Spin for Only CPU and start second CPU.S). When do you plan to add it? Or can tell me your idea and I can add it right now. Regards Yinghai Lu LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 starting... LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 starting... Bootstrap cpu setting up coherent ht domain.... done. PCI: 00:01.00 PCI: 00:01.01 PCI: 00:02.00 PCI: 00:02.01 PCI: 00:03.00 PCI: 00:04.00 PCI: 00:04.01 PCI: 00:04.02 PCI: 00:04.03 PCI: 00:04.05 PCI: 00:04.06 PCI: 00:18.00 PCI: 00:18.01 PCI: 00:18.02 PCI: 00:18.03 PCI: 00:19.00 PCI: 00:19.01 PCI: 00:19.02 PCI: 00:19.03 SMBus controller enabled Ram1 setting up CPU0 northbridge registers done. Ram2 Ram3 dcl: 08018000 Initializing memory: done Ram4 Ram5 Ram6 dimm: 50 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 51 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 52 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 53 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 54 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff dimm: 55 00: 80 08 07 0d 0a 01 48 00 04 60 70 02 82 08 08 01 10: 0e 04 0c 01 02 26 c0 75 70 00 00 48 30 48 2a 40 20: 80 80 45 45 00 00 00 00 00 3c 48 30 2d 55 64 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 a2 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 11 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff DRAM fill: 00000000-00001000 00001000 DRAM filled DRAM verify: 00000000-00001000 00001000 DRAM verified Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.02.0Fallback Tue Jun 24 02:16:37 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:01.0 [1022/7450] PCI: 00:01.1 [1022/7451] PCI: 00:02.0 [1022/7450] PCI: 00:02.1 [1022/7451] PCI: 00:03.0 [1022/7460] PCI: 00:04.0 [1022/7468] ops PCI: 00:04.0 [1022/7468] PCI: 00:04.1 [1022/7469] ops PCI: 00:04.1 [1022/7469] PCI: 00:04.2 [1022/746a] PCI: 00:04.3 [1022/746b] ops PCI: 00:04.3 [1022/746b] PCI: 00:04.5 [1022/746d] PCI: 00:04.6 [1022/746e] PCI: 00:18.0 [1022/1100] PCI: 00:18.1 [1022/1101] PCI: 00:18.2 [1022/1102] PCI: 00:18.3 [1022/1103] PCI: 00:19.0 [1022/1100] PCI: 00:19.1 [1022/1101] PCI: 00:19.2 [1022/1102] PCI: 00:19.3 [1022/1103] PCI: pci_scan_bus for bus 1 PCI: 01:09.0 [14e4/1648] PCI: 01:09.1 [14e4/1648] PCI: 01:0a.0 [1000/0030] PCI: 01:0a.1 [1000/0030] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus for bus 2 PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: 03:00.0 [1022/7464] ops PCI: 03:00.0 [1022/7464] PCI: 03:00.1 [1022/7464] ops PCI: 03:00.1 [1022/7464] PCI: 03:00.2 [1022/7463] PCI: 03:01.0 [1022/7462] PCI: 03:05.0 [105a/3373] PCI: 03:06.0 [1002/4752] PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus returning with max=03 done Allocating resources... ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:01.0 24 <- [0xfe200000 - 0xfe1fffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfe100000 - 0xfe1fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:09.0 10 <- [0xfe100000 - 0xfe10ffff] mem PCI: 01:09.0 18 <- [0xfe110000 - 0xfe11ffff] mem PCI: 01:09.1 10 <- [0xfe120000 - 0xfe12ffff] mem PCI: 01:09.1 18 <- [0xfe130000 - 0xfe13ffff] mem PCI: 01:0a.0 10 <- [0x00001000 - 0x000010ff] io PCI: 01:0a.0 14 <- [0xfe140000 - 0xfe14ffff] mem PCI: 01:0a.0 1c <- [0xfe150000 - 0xfe15ffff] mem PCI: 01:0a.1 10 <- [0x00001400 - 0x000014ff] io PCI: 01:0a.1 14 <- [0xfe160000 - 0xfe16ffff] mem PCI: 01:0a.1 1c <- [0xfe170000 - 0xfe17ffff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:02.0 1c <- [0x00003000 - 0x00002fff] bus 2 io PCI: 00:02.0 24 <- [0xfe200000 - 0xfe1fffff] bus 2 prefmem PCI: 00:02.0 20 <- [0xfe200000 - 0xfe1fffff] bus 2 mem PCI: 00:03.0 1c <- [0x00002000 - 0x00002fff] bus 3 io PCI: 00:03.0 24 <- [0xfe200000 - 0xfe1fffff] bus 3 prefmem PCI: 00:03.0 20 <- [0xfd000000 - 0xfe0fffff] bus 3 mem ASSIGN RESOURCES, bus 3 PCI: 03:00.0 10 <- [0xfe020000 - 0xfe020fff] mem PCI: 03:00.1 10 <- [0xfe021000 - 0xfe021fff] mem PCI: 03:00.2 10 <- [0xfe025000 - 0xfe0250ff] mem PCI: 03:00.2 14 <- [0xfe026000 - 0xfe02601f] mem PCI: 03:01.0 10 <- [0xfe022000 - 0xfe022fff] mem PCI: 03:05.0 10 <- [0x00002480 - 0x000024bf] io PCI: 03:05.0 14 <- [0x000024c0 - 0x000024cf] io PCI: 03:05.0 18 <- [0x00002400 - 0x0000247f] io PCI: 03:05.0 1c <- [0xfe023000 - 0xfe023fff] mem PCI: 03:05.0 20 <- [0xfe000000 - 0xfe01ffff] mem PCI: 03:06.0 10 <- [0xfd000000 - 0xfdffffff] mem PCI: 03:06.0 14 <- [0x00002000 - 0x000020ff] io PCI: 03:06.0 18 <- [0xfe024000 - 0xfe024fff] mem ASSIGNED RESOURCES, bus 3 PCI: 00:04.1 20 <- [0x000038e0 - 0x000038ef] io PCI: 00:04.2 10 <- [0x000038c0 - 0x000038df] io PCI: 00:04.5 10 <- [0x00003000 - 0x000030ff] io PCI: 00:04.5 14 <- [0x00003880 - 0x000038bf] io PCI: 00:04.6 10 <- [0x00003400 - 0x000034ff] io PCI: 00:04.6 14 <- [0x00003800 - 0x0000387f] io ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess...DEV: 00:01.0 cmd <- 07 DEV: 00:01.1 cmd <- 00 DEV: 00:02.0 cmd <- 07 DEV: 00:02.1 cmd <- 00 DEV: 00:03.0 cmd <- 07 DEV: 00:04.0 cmd <- 0f DEV: 00:04.1 cmd <- 01 DEV: 00:04.2 cmd <- 01 DEV: 00:04.3 cmd <- 00 DEV: 00:04.5 cmd <- 01 DEV: 00:04.6 cmd <- 01 DEV: 00:18.0 cmd <- 00 DEV: 00:18.1 cmd <- 00 DEV: 00:18.2 cmd <- 00 DEV: 00:18.3 cmd <- 00 DEV: 00:19.0 cmd <- 00 DEV: 00:19.1 cmd <- 00 DEV: 00:19.2 cmd <- 00 DEV: 00:19.3 cmd <- 00 DEV: 01:09.0 cmd <- 02 DEV: 01:09.1 cmd <- 02 DEV: 01:0a.0 cmd <- 03 DEV: 01:0a.1 cmd <- 03 DEV: 03:00.0 cmd <- 02 DEV: 03:00.1 cmd <- 02 DEV: 03:00.2 cmd <- 02 DEV: 03:01.0 cmd <- 02 DEV: 03:05.0 cmd <- 03 DEV: 03:06.0 cmd <- 83 done. Initializing devices... PCI: 00:04.0 init lpc_init PCI: 00:04.1 init ide_init IDE1 IDE0 PCI: 00:04.3 init PCI: 03:00.0 init USB: Setting up controller.. done. PCI: 03:00.1 init USB: Setting up controller.. done. Devices initialized totalram: 1024M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(72-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x0f Processor Model : 0x05 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x078bf9ff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0 done. CPU #0 Initialized Checking IRQ routing tables... /root/xx/xx/freebios2/src/arch/i386/boot/pirq_routing.c: 29:check_pirq_routin g_table() - irq_routing_table located at: 0x00008a20 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed Wrote linuxbios table at: 00000500 - 00000b0c checksum 916 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 Found ELF candiate at offset 0 Loading Etherboot version: 5.1.8 Dropping non PT_LOAD segment New segment addr 0x20000 size 0x34718 offset 0xb0 filesize 0x56d6 (cleaned up) New segment addr 0x20000 size 0x34718 offset 0xb0 filesize 0x56d6 Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000034718 filesz: 0x00 000000000056d6 Clearing Segment: addr: 0x00000000000256d6 memsz: 0x000000000002f042 Jumping to boot code at 0x20000 ROM segment 0x0400 length 0x03ea reloc 0x00020000 CPU 1870 Mhz Etherboot 5.1.8 (GPL) Tagged ELF (Multiboot) for [TG3] Relocating _text from: [000256e0,00054d50) to [3ffd0990,40000000) Probing pci nic... [TG3]Cannot find PowerManagement capability, aborting. [TG3]Ethernet addr: 00:E0:81:F0:18:CD Tigon3 [partno(BCM95704A7) rev 2002 PHY(5704)] (PCIX:100MHz:64-bit) Link is up at 100 Mbps, half duplex. Searching for server (DHCP)... ..Me: 192.168.1.198, Server: 192.168.1.1, Gateway 192.168.1.1 Loading 192.168.1.1:ram0_2.5_2.4.21_k8_lsi_mydisk4.elf ...(ELF)... ............. ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ............................................................................ ................................................................done Firmware type: LinuxBIOS Linux version 2.4.21 (root@tst2723_rh9) (gcc version 3.2.2 20030222 (Red Hat Lin ux 3.2.2-5)) #11 SMP Wed Jun 18 13:51:49 EDT 2003 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000b6c (reserved) BIOS-e820: 0000000000000b6c - 00000000000a0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) BIOS-e820: 0000000000100000 - 0000000040000000 (usable) 128MB HIGHMEM available. 896MB LOWMEM available. hm, page 00000000 reserved twice. On node 0 totalpages: 262144 zone(0): 4096 pages. zone(1): 225280 pages. zone(2): 32768 pages. Kernel command line: root=/dev/ram0 rw ram0_2.5_2.4.21_k8_lsi_mydisk4.elf -retad dr 0X3FFD0B34 Found and enabled local APIC! Initializing CPU#0 Detected 1793.412 MHz processor. Calibrating delay loop... 3578.26 BogoMIPS Memory: 1029284k/1048576k available (1525k kernel code, 18904k reserved, 338k da ta, 292k init, 131072k highmem) Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) Inode cache hash table entries: 65536 (order: 7, 524288 bytes) Mount cache hash table entries: 512 (order: 0, 4096 bytes) Buffer-cache hash table entries: 65536 (order: 6, 262144 bytes) Page-cache hash table entries: 262144 (order: 8, 1048576 bytes) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK. POSIX conformance testing by UNIFIX mtrr: v1.40 (20010327) Richard Gooch (rgooch(a)atnf.csiro.au) mtrr: detected mtrr type: Intel CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) Intel machine check reporting enabled on CPU#0. CPU0: AMD 02/05 stepping 08 per-CPU timeslice cutoff: 2925.75 usecs. SMP motherboard not detected. enabled ExtINT on CPU#0 ESR value before enabling vector: 00000000 ESR value after enabling vector: 00000000 Using local APIC timer interrupts. calibrating APIC timer ... ..... CPU clock speed is 1793.4469 MHz. ..... host bus clock speed is 199.2718 MHz. cpu: 0, clocks: 1992718, slice: 996359 CPU0<T0:1992704,T1:996336,D:9,S:996359,C:1992718> Waiting on wait_init_idle (map = 0x0) All processors have done init_idle CPU 0: Machine Check Exception: 0000000000000007 Bank 3: b40000000000083b at 000000fdfc000cfe Kernel panic: Unable to continue

2 1

Trying to freeze and failing ...
by ron minnich 24 Jun '03

24 Jun '03

Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set to UC' code is not fouling up the K7sem? I really do want to freeze the 1.0 tree but we're not converging. Or we almost are save for "the last few bugs". I just got some K7SEM's but won't have time to look at this for a bit -- if anyone can test this for me with the latest CVS that would be helpful. Andrew Ip, you are probably the best person to test this, can you take a look? ron

3 7

I new here
by Janek Kozicki 24 Jun '03

24 Jun '03

Hello, I just stumbled over your new webpage http://www.linuxbios.org/ I've read some of the stuff there, and I simply loved that idea. I subscribed to get a grasp of what currently is going on at the linuxBIOS development. My motherboard is Abit VP6 dual PIII, maybe at some point in the future it will get support. And I'll be the first tester ;) Anyway I must get a grasp of all this stuff to understand what's going on :) First of all - May I make some notices to the LinuxBIOS team? ;) 1. I've read FAQ. But althought I've read the whole FAQ I didn't get the answer for one question. - what is DoS ? (there are answers about how to prepare DoS, but not what is DoS by itself) - on second thought - wouldn't it be nice if you place some email addres on the webpage. for example in the FAQ section. "do you have a question not answered in the FAQ? email this question to us". If you don't want spambots to collect this email address - display it as an image with text written on it. Spambots cannot (yet) collect email addresses from images. 2. If you are interested I can offer you some little help with LinuxBIOS webpage. I'm currently working on some php scripts designed to make easy management of webpage contents (I called it GNU/enjine ;). The easy management is achieved by creating a menu file, which contains information about what is to be displayed. Now you don't have to edit the html, but just the menu. Short descripton with testing of some features is here: http://absurd.kozicki.pl:2345/~www/engine/current/ An example usage of enjine (my computer usage/load graphs made with rrdtools): http://absurd.kozicki.pl:2345/~www/rrd.eng/ best regards -- # Janek Kozicki # janek(a)thenut.eti.pg.gda.pl

1 0

Re: linuxbios
by ron minnich 24 Jun '03

24 Jun '03

On Mon, 23 Jun 2003, rickytato wrote: > Hi Ron, I'm rickytato, I want to know if the pc-chips M830LR are > supported by linuxbios. on the web site the status are unstable, but I > think that web site aren't upgrade. I am not sure any more. We'll have to ask the list. Who owns that board? ron

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