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re: [COMMIT] Infrastructure Updates 4
by YhLu 05 Sep '03

05 Sep '03

Eric, The AGP display Adapter shown out too. When enumerating the CPU 0 Link0 for 8151, it first collapse the early non-conherent device 5:0.0 ( 8151) and then assign unit id (1) to him. So the device id is change to 5:1.0. After that on bus5 there is a invalid device 5:0.0 is there.( Child of Bus 5). I wonder that We should remove that invalid device or change unit id back to 0 before calling pci_scan_bus. According to AMD datasheet, the device on bus other bus 0 can use 0 as unit id. Of' course should name it some bigger unit id and after enumerating chain, change it back to 0. It hang out after scan link2 and link0. ??? Regards YH. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Fri Sep 5 02:45:43 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled PCI: 05:00.0 No device operations PCI: pci_scan_bus for bus 6 PCI: 06:00.0 [10de/0322] enabled PCI: pci_scan_bus returning with max=06 PCI: pci_scan_bus returning with max=06 Hyper transport scan link: 0 new max: 6 Hypertransport scan link done

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A question on the SC 520
by ron minnich 05 Sep '03

05 Sep '03

My first shot at a simpler target for V2 is the AMD Elan SC520. It's as different from the K8 as I can get. I can thus test the structure of V2 and see how hard this will be. V2 is good at really complex systems such as the K8 (probably the most complex system we've ever done); how hard is it for really simple systems; how much of a burden is the "complex system" support when writing for a simple system? This is a pretty integrated chip. It can't be said to have a north/southbridge per se. I'm thinking of doing something like this: src/mainboard/jumptech/mops520 src/cpu/amd/sc520 and that would be it. No north or southbridge directories. The code to bring up the 520 is pretty straightforward, and AMD offers it all in source form, which is really helpful. It looks to be about a few tens of lines of C code for the hard-wired DRAM case, which is the first one I will try. Comments welcome. ron

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Re: [COMMIT] Infrastructure Updates 4
by YhLu 04 Sep '03

04 Sep '03

Eric, If I disable the hard_reset, it can enumerate from link2 to link0. And the 8131 on link2 and 8151 on link0 all show out. Maybe you can add MACRO to control reverse scan for AMKK8 northbridge. ( link2 then link0) But it continues to reboot. Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 19:17:58 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 0 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled Copying LinuxBIOS to ram. -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:48 收件人: ebiederman(a)lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: re: [COMMIT] Infrastructure Updates 4 Eric, In the hypertransport_scan_chain, if the hard_reset is needed, it may produce problem. Hard_reset call 8111 LPC (B1, D4, F0) reg 0x47 to trigger Reset. But it is called before pci_scan_bus. At that time the 8111 LPC is still unkown. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:30 收件人: 'ebiederman(a)lnxi.com' 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 I still have problems for s2885. Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131. Then it reboot again and agin. After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems. YH. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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re: [COMMIT] Infrastructure Updates 4
by YhLu 04 Sep '03

04 Sep '03

Eric, In the hypertransport_scan_chain, if the hard_reset is needed, it may produce problem. Hard_reset call 8111 LPC (B1, D4, F0) reg 0x47 to trigger Reset. But it is called before pci_scan_bus. At that time the 8111 LPC is still unkown. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:30 收件人: 'ebiederman(a)lnxi.com' 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 I still have problems for s2885. Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131. Then it reboot again and agin. After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems. YH. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed

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Re: [COMMIT] Infrastructure Updates 4
by YhLu 04 Sep '03

04 Sep '03

I still have problems for s2885. Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131. Then it reboot again and agin. After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems. YH. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年9月3日 20:09 收件人: YhLu 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 YhLu <YhLu(a)tyan.com> writes: > Eric, > > Please check function hypertransport_scan_chain definition and calling > parameters. > > It seems the .h and .c is not consistent. You are right. I have removed the middle parameter (something I was playing with) from northbridge.c and hypertransport.h. Some one shoot me for forgetting to include hypertransport.h in hypertransport.c And committed that. This should be the reason why the bus numbers don't automatically work on the s2885. Eric

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init_timer()
by Greg Watson 04 Sep '03

04 Sep '03

K8 developers: I've moved init_timer() from hardwaremain.c to the static initialization code in cpu/k8/cpufixup.c as it prevents PPC code from building. Please check that everything still works ok. Greg

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re: [COMMIT] Infrastructure Updates 4
by YhLu 04 Sep '03

04 Sep '03

Eric, Please check function hypertransport_scan_chain definition and calling parameters. It seems the .h and .c is not consistent. Regards YH

2 1

coding
by ron minnich 03 Sep '03

03 Sep '03

anybody object to anonymous enums? I've gotten used to them in Plan 9 and like them. Instead of this: #define FLOPPY_DEVICE 0 #define PARALLEL_DEVICE 1 #define COM2_DEVICE 2 #define COM1_DEVICE 3 #define SWC_DEVICE 4 #define MOUSE_DEVICE 5 #define KBC_DEVICE 6 #define GPIO_DEVICE 7 #define ACB_DEVICE 8 #define FSCM_DEVICE 9 #define WDT_DEVICE 10 you get this: enum { FLOPPY_DEVICE=0, PARALLEL_DEVICE, COM2_DEVICE, COM1_DEVICE, SWC_DEVICE, MOUSE_DEVICE, KBC_DEVICE, GPIO_DEVICE, ACB_DEVICE, FSCM_DEVICE, WDT_DEVICE }; The advantages I see - somewhat less prone to error - looks nicer - the big one: enums are first-class objects to the compiler, and #defines are pertty much ripped out by the compiler and disappear into constant numbers. comments? ron

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description of DoC control registers
by Niki Waibel 03 Sep '03

03 Sep '03

is there a written documentation about the DoC control registers? (2000, millennium) or do i have to find out from the linux kernel drivers? niki

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Which board?
by Jeff Noxon 03 Sep '03

03 Sep '03

I'm about to put some 1U servers together at the office. I want to use LinuxBIOS because they will be operated offsite, and it makes management easier. So I want Linux in Flash. Which Xeon boards are recommended at this point in time? Thanks Jeff

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