coreboot December 2022

coreboot@coreboot.org

28 participants
39 discussions

[coreboot - Bug #415] (New) RESOURCE_ALLOCATION_TOP_DOWN breaks edk2
by Sean Rhodes 02 May '25

02 May '25

Issue #415 has been reported by Sean Rhodes. ---------------------------------------- Bug #415: RESOURCE_ALLOCATION_TOP_DOWN breaks edk2 https://ticket.coreboot.org/issues/415 * Author: Sean Rhodes * Status: New * Priority: Low * Target version: none * Start date: 2022-09-07 * Affected versions: master ---------------------------------------- CB:41957 enabled RESOURCE_ALLOCATION_TOP_DOWN by default, which stopped edk2 from booting. The commit has been reverted, so this ticket is just to post logs. ---Files-------------------------------- resource_allocatorv4.txt (94 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #420] (New) Use standard format of TPM event log
by Krystian Hebel 07 Aug '24

07 Aug '24

Issue #420 has been reported by Krystian Hebel. ---------------------------------------- Feature #420: Use standard format of TPM event log https://ticket.coreboot.org/issues/420 * Author: Krystian Hebel * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-12 * Related links: [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementa… [2] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05… ---------------------------------------- Currently coreboot uses proprietary format for TPM event log. TCG has standardized log formats, differently for TPM1.2 (aka legacy or SHA1) [1] and TPM2.0 (aka crypto agile) [2], both of which can be parsed by Linux kernel and exposed in sysfs. I don't know of any tool outside of cbmem which can parse coreboot format; this includes payloads which may be interested in continuing chain of trust started by coreboot. Another incompatibility is caused by vboot's assignment of PCRs. Roles of PCRs are roughly specified by TCG in both of mentioned documents, they are more or less compatible with each other, but not with current coreboot code. These changes could break assumptions made by existing platforms, so they should be made as Kconfig options. This is a tracking issue to collect subtasks that need to be done in order to support standard event log formats. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #433] (New) Unify TPM drivers in coreboot
by Michał Żygowski 24 Apr '24

24 Apr '24

Issue #433 has been reported by Michał Żygowski. ---------------------------------------- Feature #433: Unify TPM drivers in coreboot https://ticket.coreboot.org/issues/433 * Author: Michał Żygowski * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-24 ---------------------------------------- Add an option to compile all drivers for TPM 1.2, 2.0 TIS and CRB. The motivation is to not build multiple coreboot ROMs for each possible TPM supported by the platform. The tasks would include: - runtime TPM detection (probing TPM_INTF_CAPABILITY and TPM_INTERFACE_ID) - rename the TPM driver functions, make them static and expose them as a driver structure, e.g. struct tpm_driver { void (*init)(void); int (*open)(void); int (*close)(void); int (*sendrecv)(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len); } - based on the detected TPM, hook the tpm_driver functions to provide the global TPM API: tis_open, tis_close, tis_init, tis_sendrecv. Some additional API to get vendor/device name could also be considered. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed
by Mike Banon 21 Feb '24

21 Feb '24

If I use a default config for i440fx/piix4, building a 16MB ROM works fine, but 32MB or 64MB doesn't work anymore: ... CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug OBJCOPY cbfs/fallback/romstage.elf CREATE build/mainboard/emulation/qemu-i440fx/cbfs-file.vqaXlP.out (from /home/my_custom_path_to/coreboot/.config) CC+STRIP src/lib/cbfs_master_header.c OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.elf OBJCOPY bootblock.raw.bin Created CBFS (capacity = 33553892 bytes) BOOTBLOCK CBFS cbfs_master_header CBFS fallback/romstage cbfstool: /home/my_custom_path_to/coreboot/util/cbfstool/cbfstool.c:1145: cbfstool_convert_mkstage: Assertion `IS_HOST_SPACE_ADDRESS(host_space_address)' failed. make: *** [Makefile.inc:1116: build/coreboot.pre] Aborted -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Re: Deprecation of the Intel Quark SoC
by Łukasz Jeleń 02 Mar '23

02 Mar '23

Hi, My background is low level ARM and I want to get familiar with low level x86. I bought galileo v1 because it is cheap, small and handy x86 board. I have built coreboot code. It does not boot "out of the box". I had to add rmu.bin into coreboot.rom. With this logging on uart works. It seems SD/MMC controller also works. Now I'm struggling with: [INFO ] CBFS: Found 'fspm.bin' @0x31c40 size 0x2f000 in mcache @0x80004f84 [ERROR] CBFS ERROR: 'fspm.bin' allocation failure [EMERG] FSPM not available or failed to load! Regards, Łukasz

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Recent board removal for deprecated features LEGACY_SMP_INIT and RESOURCE_ALLOCATOR_V3
by Paul Menzel 06 Feb '23

06 Feb '23

Dear coreboot folks, Two days ago, on November 7th, the change-sets of the topic *drop_LEGACY_SMP_INIT* [1] were submitted after being created on November 2nd [2]. The removal was announced on the list some time ago and was documented in the release notes. 1. RESOURCE_ALLOCATOR_V3 in the 4.16 release notes [3] 2. LEGACY_SMP_INIT in the 4.16, 4.17, and 4.18 release notes [4] (I think that planned deprecations should to be listed in each release note.) Despite the missing RESOURCE_ALLOCATOR_V3 deprecation announcement in 4.17 and 4.18, everything was done formally correct, nevertheless I would have wished, more time would have been given and the actions would have been announced once more on the mailing list. My understanding was always, that code removal will be handled more leniently, if the required changes are being worked on. This was the case here for parallel SMP init [5] and resource allocator v4 [6]. Some change-sets even had a +1 or +2. The request for testing was also fulfilled by the users. Some of the change-sets were even authored by “non-AGESA“ folks, which was awesome to see. Letting this effort go to waste without documenting somewhere, what needed to be done to finish these change-sets makes me sad. 3mdeb also invested resources into implementing some of the features. The last thing I noticed, that at least for the PC Engines board removal, the approval of the maintainers listed in `MAINTAINERS` was not given, and should have been waited for. The +2 itself were also by developers normally not (very) active with AMD AGESA Open Source boards. The points above are just my observations, and, hopefully, things can improve in the future to avoid bad feelings. I am thankful to everyone working on coreboot, and I also understand the frustration of having to maintain several code paths. Although I own and run two of the removed boards, I am fine to move to the branch *4.18_branch* although I am not happy about it, as branches also increase maintenance burden. The main reason for writing this message is to ask, if entities (read 3mdeb) have big interest in getting part of the boards back into the master branch, so that the already made investments are not in vain, and nobody is alienated from working upstream. If that is a goal, this effort should be coordinated as reverting commits is going to become harder and harder. mb/aopen/dxplplusu (Intel) is already worked on to be put back into the master branch [7]. Kind regards, Paul [1]: https://review.coreboot.org/q/topic:drop_LEGACY_SMP_INIT [2]: https://review.coreboot.org/c/coreboot/+/69111/2 [3]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/tags/4.18/Docum… [4]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/tags/4.18/Docum… [5]: https://review.coreboot.org/c/coreboot/+/64892 "cpu/amd/family15: Use parallel_mp init" [6]: https://review.coreboot.org/c/coreboot/+/53990 "nb/amd/agesa/family15tn: Enable RESOURCE_ALLOCATOR_V4" [7]: https://review.coreboot.org/c/coreboot/+/69339 "Revert "mb/aopen/dxplplusu: Remove board""

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[coreboot - Bug #440] (New) superiotool tells you to run it as root and stops even when ran as root
by J Nky 23 Jan '23

23 Jan '23

Issue #440 has been reported by J Nky. ---------------------------------------- Bug #440: superiotool tells you to run it as root and stops even when ran as root https://ticket.coreboot.org/issues/440 * Author: J Nky * Status: New * Priority: Normal * Target version: none * Start date: 2022-11-24 * Affected versions: 4.15 * Affected OS: ubuntu 22.10 ---------------------------------------- On ubuntu 22.10: **sudo superiotool** iopl: Function not implemented Superiotool must be run as root. superiotool tells you to run it as root and stops even when ran as root -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot/LinuxBoot on Supermicro server boards
by Paul Menzel 23 Jan '23

23 Jan '23

Dear coreboot folks, A colleague made me aware of the presentation *The OSF on Supermicro's platform* [1] by the Supermicro employees Hancock Chang and Simon Chou¹ at the OCP Global Summit 2022 this October. This is great news. I would have loved to also read about this on the coreboot mailing list. In the talk, the board Supermicro X12SPW is mentioned, and that it’s planned for the X13 series. One of our suppliers responded though, that systems with coreboot are currently not generally available, but it’s something Supermicro offers to ODMs or for projects with large volumes. The slide *Call to Action* contains: > Come and collaborate with Supermicro Collaboration would be great. A first step would be, if Supermicro (engineers) would get in touch with the coreboot project/community on the mailing list, and also upstreamed their work and contributed their improvements. Judging from the presented times, there is still a lot of potential to unlocked, and where the coreboot community already has a lot of experience in to share to make sure, the Supermicro boards work even better. Kind regards, Paul PS: OpenBMC patches are already being sent upstream [2]. ¹ Hopefully correct addresses in Cc. At least my test message did not bounce. [1]: https://www.youtube.com/watch?v=U_WO-_np9wQ [2]: https://lore.kernel.org/openbmc/20221229100155.2954455-1-ryans@supermicro.c…

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[coreboot - Bug #392] (New) Coreboot 4.16 & 4.17 - SeaBios Windows 10 BSOD "ACPI Error"
by Pawel Radomychelski 15 Jan '23

15 Jan '23

Issue #392 has been reported by Pawel Radomychelski. ---------------------------------------- Bug #392: Coreboot 4.16 & 4.17 - SeaBios Windows 10 BSOD "ACPI Error" https://ticket.coreboot.org/issues/392 * Author: Pawel Radomychelski * Status: New * Priority: High * Category: board support * Target version: 4.17 * Start date: 2022-06-18 * Affected versions: 4.16, 4.17, master * Affected hardware: Lenovo ThinkPad X230 Tablet * Affected OS: Windows 10 ---------------------------------------- Since CoreBoot 4.16 my Windows 10 cant boot from SeaBios, i get BSOD with "ACPI Error" very early. Don't know which commit exactly brakes ACPI, but i can say, that in my CoreBoot 4.15 Image from 11/09/2021 Windows 10 is booting just fine from SeaBIOS. Some time later under CoreBoot 4.16 i saw that windows is BSODing. Tried yesterday with CoreBoot 4.17 and its still broken. I think, since CB4.16 there is something broken in ACPI. As i read, the problem is, that ACPI reserves some memory area, which in Windows is reserved for the system. This [[https://ticket.coreboot.org/issues/327]] seems to be a similar problem, but the guy is using TianoCore instead of SeaBIOS. Changing the line OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) to OperationRegion (OPRG, SystemMemory, ASLS, 0x1000) doesnt fix it for SeaBios, but fix it for TianoCore. ---Files-------------------------------- dmesg_cb415.txt (78.9 KB) dmesg_cb417.txt (79.9 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #436] (New) Berknip doesn't want to boot with the built image
by Balazs Vinarz 15 Jan '23

15 Jan '23

Issue #436 has been reported by Balazs Vinarz. ---------------------------------------- Bug #436: Berknip doesn't want to boot with the built image https://ticket.coreboot.org/issues/436 * Author: Balazs Vinarz * Status: New * Priority: Normal * Target version: none * Start date: 2022-11-01 * Affected hardware: Google Berknip (Zork) * Affected OS: NA ---------------------------------------- I was trying to flash the build 4.18 Coreboot image for my HP c645, as only RW_LEGACY image was available for this machine at MrChromebox. Now the machine, heat's the CPU if I plug in the USB-C adapter or the battery, but shows no image at all. I can manage to flash back the original image, I just wanted to highlight this. Build logs are added as attachments. I compared the CBFS regions side by side and it seems: * Google build only 1 microcode blob, while I have 3 and * the VBGFX.bin is missing at my build, however however the optionroms for the iGP is added. ``` diff apu/amdfw 0x5aafc0 raw 13155 | apu/amdfw 0x5aafc0 amdfw 12574 bootblock 0x77afc0 bootblock 655 | build_info 0x27e00 raw cbfs master header 0x0 cbfs header | cbfs_master_header 0x0 cbfs header config 0x2b840 raw 8 | config 0x27940 raw 4 cpu_microcode_blob.bin 0xd5c0 microcode 96 | cpu_microcode_8180.bin 0x7a80 microcode 32 (empty) 0x48280 null 33 | cpu_microcode_8181.bin 0x8740 microcode 32 (empty) 0x52d3c0 null 5150 | cpu_microcode_8201.bin 0x9400 microcode 32 (empty) 0x6ec300 null 5848 | (empty) 0x6de000 null 7085 fallback/dsdt.aml 0x2bf00 raw 157 | (empty) 0x81c00 null 54117 fallback/payload 0x511a00 simple elf 1129 | fallback/dsdt.aml 0x27ec0 raw 155 fallback/ramstage 0xfbc0 (unknown) 1136 | fallback/payload 0x6fac0 simple elf 718 fallback/romstage 0x80 (unknown) 545 | fallback/ramstage 0xa0c0 stage 1208 > fallback/romstage 0x80 stage 310 FMAP REGION: COREBOOT FMAP REGION: COREBOOT font.bin 0x4e4a80 raw 50 | fspm.bin 0x2bc00 fsp 996 fspm.bin 0x2fcc0 fsp 994 | fsps.bin 0x44180 fsp 697 fsps.bin 0x48fc0 fsp 692 | header_pointer 0x78afc0 cbfs header locale_ar.bin 0x46dcc0 raw 789 < locale_bg.bin 0x157d40 raw 1109 < locale_bn.bin 0x1185c0 raw 981 < locale_ca.bin 0x1d9e40 raw 969 < locale_cs.bin 0x42c980 raw 954 < locale_da.bin 0x1f1980 raw 938 < locale_de.bin 0x9e1c0 raw 1121 < locale_el.bin 0xf95c0 raw 1269 < locale_en.bin 0x4fd040 raw 843 < locale_es-419.bin 0x2b1200 raw 1058 < locale_es.bin 0x4145c0 raw 991 < locale_et.bin 0x269400 raw 858 < locale_fa.bin 0x4b0900 raw 787 < locale_fi.bin 0x2cb000 raw 902 < locale_fil.bin 0x1a8500 raw 1005 < locale_fr.bin 0x24ee40 raw 1078 < locale_gu.bin 0x3e8f40 raw 824 < locale_he.bin 0xd1340 raw 559 < locale_hi.bin 0x221780 raw 796 < locale_hr.bin 0x38a380 raw 970 < locale_hu.bin 0xdee00 raw 1084 < locale_id.bin 0x3a1f00 raw 924 < locale_it.bin 0x372a00 raw 965 < locale_ja.bin 0x297e40 raw 1032 < locale_kn.bin 0x33f1c0 raw 1190 < locale_ko.bin 0x443ec0 raw 646 < locale_lt.bin 0x3fd1c0 raw 951 < locale_lv.bin 0x4e5e40 raw 946 < locale_ml.bin 0x4c3d40 raw 1343 < locale_mr.bin 0x318700 raw 733 < locale_ms.bin 0x35c340 raw 917 < locale_nb.bin 0x747c0 raw 898 < locale_nl.bin 0x481140 raw 969 < locale_pl.bin 0x2e1100 raw 1092 < locale_pt-BR.bin 0x3d0580 raw 1006 < locale_pt-PT.bin 0x208840 raw 1021 < locale_ro.bin 0x498c40 raw 973 < locale_ru.bin 0x234f00 raw 1062 < locales 0x48180 raw 1 < locale_sk.bin 0x3b88c0 raw 974 < locale_sl.bin 0xb9840 raw 969 < locale_sr.bin 0x453bc0 raw 1066 < locale_sv.bin 0x172f40 raw 951 < locale_ta.bin 0x18a380 raw 1231 < locale_te.bin 0x27e3c0 raw 1049 < locale_th.bin 0x146d00 raw 695 < locale_tr.bin 0x302ec0 raw 880 < locale_uk.bin 0x1c0e40 raw 1023 < locale_vi.bin 0x130580 raw 919 < locale_zh-CN.bin 0x8a700 raw 804 < locale_zh-TW.bin 0x32a5c0 raw 849 < Name Offset Type Size Name Offset Type Size pci1002,15d8,c1.rom 0x59ec0 optionrom 542 | payload_config 0x81400 raw 16 pci1002,15dd,c4.rom 0x67340 optionrom 542 | payload_revision 0x81ac0 raw 2 revision 0x2bc00 raw 6 | pci1002,15d8,c1.rom 0x55240 optionrom 542 vbgfx.bin 0x2fbc00 raw 292 | pci1002,15dd,c4.rom 0x62680 optionrom 542 > revision 0x27b00 raw 7 ``` ---Files-------------------------------- build_berknip_20221031.log (58.6 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot December 2022