coreboot September 2021

coreboot@coreboot.org

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33 discussions

[coreboot - Feature #320] (New) T440p: Does not display fan RPM
by coreboot＠fe80.eu 04 Sep '21

04 Sep '21

Issue #320 has been reported by Daniel Kulesz. ---------------------------------------- Feature #320: T440p: Does not display fan RPM https://ticket.coreboot.org/issues/320 * Author: Daniel Kulesz * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- With the OEM firmware, the fan RPM are displayed in the `sensors` output in Linux. After flashing coreboot, this value is no longer displayed. The CPU temperatures etc. still work fine, only the fan RPMs are missing. Would be great to have it. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #319] (New) denverton_ns: Add ASL to support Linux pinctrl driver (GPIO controller)
by coreboot＠fe80.eu 02 Sep '21

02 Sep '21

Issue #319 has been reported by King Sumo. ---------------------------------------- Feature #319: denverton_ns: Add ASL to support Linux pinctrl driver (GPIO controller) https://ticket.coreboot.org/issues/319 * Author: King Sumo * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- ASL code to support the Linux pinctrl driver is missing for denverton_ns platform, the below patch adds the very basic functionality in order to Linux driver find the GPIO controller via INTC3000 APCI id: https://review.coreboot.org/c/coreboot/+/56975 soc/intel/denverton_ns: Add GPIO controller ASL Add support for the pinctrl denverton Linux driver which provides an interface that allows configuring of Intel Denverton SoC pins and using them as GPIOs. Test using the sysfs interface: - Load the pinctrl-denverton module, sysfs interface available in the /sys/kernel/debug/pinctrl/INTC3000\:00 folder. - Export the GPIO (here we are using GPIO_10): ~> cd /sys/kernel/debug/pinctrl/INTC3000\:00/ ~> grep GPIO_10 pinconf-pins pin 139 (GPIO_10): input bias disabled ~> cat gpio-ranges GPIO ranges handled: 0: INTC3000:00 GPIOS [358 - 511] PINS [0 - 153] ~> echo $((358+139)) > /sys/class/gpio/export - Above GPIO's are starting at 358 with GPIO_10 at 139 offset, the sysfs folder for controlling the pin will be /sys/class/gpio/gpio497 (358+139). - Input mode: ~> cd /sys/class/gpio/gpio497 ~> echo in > direction ~> cat value 0 ~> cat value 1 - Output mode: ~> cd /sys/class/gpio/gpio497 ~> echo out > direction ~> echo 1 > value ~> echo 0 > value -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #318] (New) denverton_ns: Fix MRC cache write
by coreboot＠fe80.eu 02 Sep '21

02 Sep '21

Issue #318 has been reported by King Sumo. ---------------------------------------- Bug #318: denverton_ns: Fix MRC cache write https://ticket.coreboot.org/issues/318 * Author: King Sumo * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- The RW_MRC_CACHE write is broken in denverton_ns platforms. More info: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/26Y… https://review.coreboot.org/c/coreboot/+/57033 (patch set as abandoned, it was already agreed with Mariusz to proceed the codereview process). -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot September 2021