coreboot September 2021

coreboot@coreboot.org

42 participants
33 discussions

Intel® FSP External Architecture Specification v2.3 Has Been Released
by Desimone, Nathaniel L 24 Sep '21

24 Sep '21

Hi Everyone, We are pleased to announce that the FSP External Architecture Specification v2.3 has been posted to https://www.intel.com/fsp! Highlights * FSP_NON_VOLATILE_STORAGE_HOB2 – A new architectural HOB has been added for storage of MRC training data. While this HOB serves the same purpose as the original FSP_NON_VOLATILE_STORAGE_HOB, it allows >64KB of MRC training data to be stored. Some of Intel’s upcoming designs will require the storage of >64KB of MRC training data, so this addition is being made in advance. Bootloaders should practice defensive programming and first search for FSP_NON_VOLATILE_STORAGE_HOB2, and only search for FSP_NON_VOLATILE_STORAGE_HOB if the former is not found in the HOB list. This algorithm will guarantee compatibility with all FSP 2.x specification versions. * FSP Version Numbers – A new ExtendedImageRevision field has been added to the FSP_INFO_HEADER. This expands the size of the Revision and Build Number fields of the FSP version number from 8 bits to 16 bits. This is done by adding a high-order byte to each of those fields. If the ExtendedImageRevision field is present, then the FSP version number is decoded as follows: Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0] Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8] Minor Version = ImageRevision[23:16] Major Version = ImageRevision[31:24] Roadmap Both Meteor Lake and Sapphire Rapids will require storage of >64KB of MRC training data. Therefore, we recommend that bootloaders plan to have support for FSP 2.3 ready by early next year. Does Anything Need to Change in coreboot? Supporting future Intel SoCs will require some changes. At a minimum, coreboot will need to be modified to support the new FSP_NON_VOLATILE_STORAGE_HOB2. Additionally, it is recommended that coreboot be modified to include the ExtendedImageRevision field when printing the FSP version number. This is not strictly required from a functional standpoint, but without it the FSP version number in the boot log will not be accurate.

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coreboot for Intel Xeon server processor
by Jonathan Zhang (Infra) 23 Sep '21

23 Sep '21

Hi colleagues, I am glad to announce that coreboot for Intel Xeon server processor has reached a major milestone: it is ready for the general development communities to have fun with. The FSP/coreboot/LinuxBoot stack for OCP (Open Compute Project) DeltaLake server was accepted by OCP OSF (Open System Firmware) project, and is made public at https://github.com/opencomputeproject/OpenSystemFirmware. For details, please check out https://doc.coreboot.org/mainboard/ocp/deltalake.html. Also the MAINTAINERS file was updated. If you have any question/suggestion, please reach out to the DeltaLake server and/or xeon-sp soc maintainers. Some additional notes: * The build system to build coreboot, Linux kernel, u-root, and to stitch the final image, is an open source project: https://github.com/facebookincubator/osf-builder * All the necessary Intel binary blobs are available with Intel redistributable licenses. DeltaLake server will be a great vehicle for engineering projects such as: * Server host firmware feature development. * Development for processor features that show up in server first, such as split IIO. If you need access to DeltaLake server, please reach out to the maintainers. I am also excited that 9 Elements volunteered to maintain the OSF DeltaLake code base, including coreboot. Going forward 9 Elements will continue to improve the code base, rebase to coreboot upstream tip, run tests and make periodic releases. We look forward to commercial success as well. All of these would not happen without coreboot community’s help, you guys rock! PS. Facebook team is looking for help. If you are interested, please check out the coreboot job board https://www.coreboot.org/jobs.html Thank you, Jonathan

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Question on loading SELF payload
by Ni, Ray 23 Sep '21

23 Sep '21

Hi, I am studying how coreboot loads the SELF format payload. From load_payload_segments() in src/lib/self_boot.c, the SELF payload is not relocated to a range of free memory. Which means the SELF payload should pick proper "segment.load_addr" for each segment, otherwise the payload may corrupt the critical memory region. coreboot may not run in background when control is transferred to payload, but before that, 1. the coreboot code that does the payload loading 2. stack may overlap with segment.load_addr of payload. Is my understanding correct? If yes, is there a recommended memory map (where is stack, where is coreboot ramstage, where is payload)? Thanks, Ray

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Help debugging qemu + coreboot using GDB
by Ni, Ray 23 Sep '21

23 Sep '21

Hi experts, I built a coreboot image with following steps for tracing coreboot ramstage flow: 1. make menuconfig --- CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y CONFIG_GDB_STUB=y CONFIG_GDB_WAIT=y --- 1. make crossgcc-i386 2. make Then I start gdb: 1. gdb 2. (gdb) file /mnt/e/work/coreboot/build/cbfs/fallback/ramstage.debug Reading symbols from /mnt/e/work/coreboot/build/cbfs/fallback/ramstage.debug... 1. (gdb) target remote:1234 Then I start QEMU: 1. qemu-system-i386 --bios build/coreboot.rom -nographic -M q35 -s --- tty out put as below --- ... Timestamp - finished loading ramstage: 627985288 BS: postcar times (exec / console): total (unknown) / 80 ms $S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02# ------------ (The "$S02#B5" repeats infinitely. I guess it's to report a stop event to GDB.) The GDB successfully connects to coreboot. "disassemble $eip, +20" works fine. "n" command doesn't work. (gdb) n Cannot find bounds of current function What mistake I might make? Thanks, Ray

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Mailing list archive not updating
by Branden Waldner 23 Sep '21

23 Sep '21

I was just checking the mailing list archive and noticed that it isn't showing any new messages since September 9. I wasn't able to determine if there was a mailing list admin address to send this to, so I hope just sending it to the list is okay. (I did see this "mailman(a)coreboot.org alias for mailman admins" while searching, but wasn't sure about it, since it doesn't actually show up on the available lists page.)

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How to enable SMMStore on MinowboardMax
by zahra rahimkhani 22 Sep '21

22 Sep '21

Hello I am trying to enable NVRAM for MainnoMax for the 4.11 branch. I am trying to save persistence config in SOC E3825. (It has a MC146818B-compatible 242 bytes of battery-backed RAM). I enabled the following options in coreboot 4.11 branch: - Use CMOS for configuration values - Load default config values on each boot And tested whether the configuration made by nvramcui (as my second mayload) is persistent across power-offs with no luck. I have the following questions and I would appreciate it if anyone can answer any of these questions: 1.How to enable coreboot to save configuration on MinnowMAX? 2.With the battery connected to the board, is it correct to use nvramcui to check persistent configuration? 3. I read about SMMSTORE as a way to store configuration changes in BIOS without having an actual EEPROM storage but I don't know if I have to enable it explicitly if my board doesn't support it. 4. How one can add SMMSTORE support for SoCs like Intel E3800 families. Also I would be grateful if anyone can send me links to investigate any further.

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T430: Flashing using plug contacts instead of fully disassembling the laptop
by Daniel Kulesz 21 Sep '21

21 Sep '21

Hi, I plan to flash a Thinkpad T430. According to an article in the german "golem.de" magazine [1] accessing the flash via SPI is possible by connecting the wires from the SPI flasher to plug contacts on the upper side of the board - without disassembling the whole device. Unfortunately, I was unable to find the details regarding these contacts neither in the coreboot docs nor anywhere else. Did I look in the wrong places or is this simply not publically documented? Cheers, Daniel [1] https://www.golem.de/news/coreboot-und-nitrokey-mein-acht-jahre-alter-lapto…

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custom board profile
by Brian Milliron 21 Sep '21

21 Sep '21

So now that I have the GPIO for my board, what else is needed? How do I setup a custom board profile in coreboot? How much debug/testing would be needed? How would that be done?

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Fwd: Denverton: NVMe not detected when serial console logs are disabled
by Sumo 21 Sep '21

21 Sep '21

Hi Paul, When logs are (almost) disabled the error isn't shown, so if I add the delay with logs disabled the log output will have almost no difference at all. Following are the logs, including a log with Coreboot debug enabled + no delay. For all logs FSP loglevel is set to NoDebug: - nvme-err.log : no delay; coreboot debug_level=Error; NVMe error: at the end of the log is shown the error in the UEFI FW: ERROR: C40000002:V02010007 I0 93B80004-9FB3-11D4-9A3A-0090273FC14D 7E90A998; - nvme-ok-delay.log : 20ms delay; coreboot debug_level=Error; NVMe ok; - nvme-ok.log : no delay; coreboot debug_level=Spew; NVMe ok: the coreboot log output is enough to make NVMe work properly; The NVMe is in the root port 00:0b.0, it is shown as 04:00.0 Thanks, Sumo On Mon, Aug 16, 2021 at 2:57 PM Paul Menzel <pmenzel(a)molgen.mpg.de> wrote: > Dear Sumo, > > > Am 16.08.21 um 18:38 schrieb Sumo: > > > The NVMe is not detected when serial console logs are disabled, I mean by > > setting both Coreboot log_level=Error (or less) and FSP > > PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then > > further on the device is not listed in the UEFI FW (same issue shown in > > either CorebootPayloadPkg or UefiPayloadPkg). When Linux boots the device > > appears normally. > > > > The problem is fixed by adding a small delay inside dev_enumerate() - a > > 20ms delay at the very beginning of the function is enough. I'm wondering > > if there is a better solution for this, the device is already defined in > > the devicetree.cb (set as on). Maybe coreboot is too fast and the NVMe is > > still booting up - or the PCIe link is still training, not sure. Coreboot > > doesn't retry if the device is not detected right away? > > Please share the logs without and with the delay. > > > Kind regards, > > Paul >

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Coreboot on newer laptops
by Brian Milliron 18 Sep '21

18 Sep '21

I've run into 2 problems with trying to set up coreboot for an HP Probook 440 G7. The first is that I don't see this model listed as an option in the menuconfig. It is a newer Intel Cometlake CPU/chipset and most of what I see listed as options are much older machines. Is there a "generic cometlake" config I can try or am I just out of luck on this? The 2nd problem is that cbfstool doesn't recognize the bios dump I did from the mainboard. I get the error "Selected image region is not a valid CBFS." I'm pretty sure the the dump is valid because I can read it using the Intel FIT tool or ME_Analyzer. I'm going to need to pull the various binary blobs out of the current firmware and this is the only way I know how. Is there another option here?

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coreboot September 2021