September 2021 - coreboot - mail.coreboot.org

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Sept. 14, 2021

Sept. 14, 2021

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1462119: Resource leaks (RESOURCE_LEAK) /src/soc/intel/common/block/acpi/pep.c: 68 in read_pmc_lpm_requirements() ________________________________________________________________________________________________________ *** CID 1462119: Resource leaks (RESOURCE_LEAK) /src/soc/intel/common/block/acpi/pep.c: 68 in read_pmc_lpm_requirements() 62 } 63 64 if (info) { 65 info->addr = (uint8_t *)reg; 66 info->buffer_size = register_count * sizeof(uint32_t); 67 } >>> CID 1462119: Resource leaks (RESOURCE_LEAK) >>> Variable "reg" going out of scope leaks the storage it points to. 68 } 69 70 /* 71 * For now there is only one disabled non-existent device, because Windows 72 * expects at least one device and crashes without it with a bluescreen 73 * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Using cmos.default / nvramtool?
by Rafael Send Sept. 14, 2021

Sept. 14, 2021

Hi all- I'm trying to set gfx_uma_size on my X210. From what I can tell, I need to either use nvramcui / nvramtool to set this, or add a cmos.default file. However, I'm not clear on how to do this correctly. If I just invoke nvramtool, I'm told that this coreboot was built without selecting "CONFIG_USE_OPTION_TABLE, which is not found in menuconfig. How do I go about creating &using a proper cmos.layout file for my machine? Thanks, R

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Re: New Kabylake-U Laptop (Acer Aspire F5-573)
by Benjamin Doron Sept. 12, 2021

Sept. 12, 2021

Hi, The return value 0x80000007 is EFI_DEVICE_ERROR, which is unfortunately for us, not very specific. The schematics will be a big help to you, if you can get them. However, you can probably manage without them. There are 3 BIOS images in the update binary from Acer. I took the liberty of assuming the relevant one was the 8 MiB file, as your SPI flash is 64 Mb. I've checked this image, and while its silicon configuration modules now more closely align with Intel's code (*OpenBoardPkg and *BoardPkg, MinPlatformPkg and reference code), so the work I've done for an Acer Skylake laptop doesn't help you, the theory is the same. The relevant modules for setting FSP-M configuration are BoardConfigInitPreMem and possibly PlatformInitPreMem. Since the RCOMP resistors and targets have a known structure (3 and 5 UINT16s, also with a somewhat predictable pattern), a good way to skip a lot of reverse engineering is to search a hexdump for known/common values, or eyeball the .data section. You may want to do this in IDA (costly, proprietary) or Ghidra (free, open-source), so that you can follow the references the code makes to the variables. I found some possible RCOMP resistors in BoardConfigInitPreMem, which brings us to 1, maybe 2, relevant functions. Depending on the board ID, the function loaded at 0xFFF15F48 will assign SpdAddressTable, DqByteMap, DqsMapCpu2Dram, RcompResistors, RcompTargets and others. coreboot boards generally ignore Dqs settings these days (except for LPDDR3/4, as I understand), so I'll just give you the possible RCOMP values, as I see them: - RCOMP targets: { 100, 40, 40, 23, 40 }, or { 100, 40, 20, 20, 26 }. Apparently, there is also { 60, 26, 20, 20, 26 }, but this looks different to what I've seen. - RCOMP resistors: { 200, 81, 162 }, or { 121, 75, 100 }, or { 121, 81, 100 } Board ID appears to be determined by PCD (essentially, UEFI global variables), so you should try dumping the PCD database with PcdGet from https://github.com/jyao1/EdkiiShellTool in a UEFI shell. By the way, according to the code you also may have an (unpopulated) SPD at 0x50 (0xA0 in the code, this is just because the SMBUS address was shifted 1 bit left into the 8-bit address form. They are equivalent). You also may need to set CaVrefConfig. "2" should be the correct value for DDR4. You should probably check that DqPinsInterleaved is correct, it's easiest if you can get this from the schematics. Best regards, Benjamin

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Build breakage
by tcullen2018 Sept. 12, 2021

Sept. 12, 2021

Hi, I'm running into a problem following the steps at https://doc.coreboot.org/tutorial/part1.html on an Ubuntu 21.04 based system. The host compiler is gcc 10.3 and apparently CoreBoot has installed gcc 8.3.0 for its own usage but seems to be missing some required parts. Everything is good up until: tcullen@alien:~/src/coreboot$ make -C payloads/coreinfo ... LPGCC coreinfo.bin /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: build/cpuinfo_module.o: in function `cpuinfo_module_init': cpuinfo_module.c:(.text+0x45e): undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: build/timestamps_module.o: in function `timestamp_print_entry.constprop.1': timestamps_module.c:(.text+0x153): undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: timestamps_module.c:(.text+0x190): undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(timer.libc.o): in function `get_cpu_khz_xtal': /home/tcullen/src/coreboot/payloads/libpayload/arch/x86/timer.c:121: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/libpayload/arch/x86/timer.c:121: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(timer.libc.o):/home/tcullen/src/coreboot/payloads/libpayload/arch/x86/timer.c:78: more undefined references to `__udivdi3' follow /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(printf.libc.o): in function `print_number': /home/tcullen/src/coreboot/payloads/libpayload/libc/printf.c:261: undefined reference to `__udivmoddi4' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(time.libc.o): in function `update_clock': /home/tcullen/src/coreboot/payloads/libpayload/libc/time.c:59: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/libpayload/libc/time.c:64: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/libpayload/libc/time.c:67: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(time.libc.o): in function `arch_ndelay': /home/tcullen/src/coreboot/payloads/libpayload/libc/time.c:166: undefined reference to `__udivdi3' /home/tcullen/src/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/8.3.0/../../../../x86_64-elf/bin/ld.bfd: /home/tcullen/src/coreboot/payloads/coreinfo/libpayload/libpayload.a(time.libc.o): in function `timer_us': /home/tcullen/src/coreboot/payloads/libpayload/libc/time.c:185: undefined reference to `__udivdi3' collect2: error: ld returned 1 exit status make: *** [../libpayload/Makefile.payload:91: build/coreinfo.bin] Error 1 make: Leaving directory '/home/tcullen/src/coreboot/payloads/coreinfo' Regards, Tim Cullen Sent with [ProtonMail](https://protonmail.com/) Secure Email.

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ECC in native ram init? (sandy/ivy)
by Matt B Sept. 11, 2021

Sept. 11, 2021

Greetings, I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work. In the unofficial mapping [1] it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first) It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there? I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS. [2] Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me. [1] https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html Sincerely, -Matthew Bradley

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Currently broken devicetrees (was Re: X200 dock has been broken since November 2019)
by Nico Huber Sept. 7, 2021

Sept. 7, 2021

Hi all, that we had another case of a missing-device-below-chip in a devicetree made me write a patch for `sconfig` [1]. Now that it's checking for the issue, that uncovered a few (31) more cases [2] that need to be fixed before upstream can benefit from the patch. Please help to fix the devicetrees. Note, `sconfig` currently doesn't print the file name of override trees, e.g. when it says SCONFIG mainboard/.../devicetree.cb line 10: end: syntax error that might as well refer to line 10 in an override tree. Nico [1] https://review.coreboot.org/c/coreboot/+/51119 [2] https://qa.coreboot.org/job/coreboot-gerrit/164572/ Failing boards: board.AMD_BILBY board.AMD_CEREME board.AMD_MANDOLIN board.GETAC_P470 board.GOOGLE_BRYA0 board.GOOGLE_FALCO board.GOOGLE_PEPPY board.GOOGLE_WOLF board.KONTRON_BSL6 board.LENOVO_R500 board.LENOVO_T430S board.LENOVO_T431S board.LENOVO_T520 board.LENOVO_T530 board.LENOVO_W530 board.LENOVO_X1 board.LENOVO_X220 board.LENOVO_X220I board.LENOVO_X220_MRC_BIN board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS board.LENOVO_X230 board.LENOVO_X230S board.LENOVO_X230T board.LENOVO_X301 board.LENOVO_X60 board.RODA_RK886EX board.SIEMENS_BOXER26

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[coreboot - Bug #321] (New) NVME in X16 port issue
by coreboot＠fe80.eu Sept. 7, 2021

Sept. 7, 2021

Issue #321 has been reported by Francois Ollonois. ---------------------------------------- Bug #321: NVME in X16 port issue https://ticket.coreboot.org/issues/321 * Author: Francois Ollonois * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- I have used latest git version of coreboot to build a rom for my ASUS P5QL-EM. I have some strange behavior: I use a **X16 nvme** Adapter in the X16 graphic card slot. I also want to use an add-on gpu card (nvidia GT710 **PCIe X1**) to be able to use higher resolution displays. With the bare board without any card everything works fine, but when I plug in the nvme adapter card with ssd, only the VGA output is working, but it is shiftet one character to the left. HDMI and DVI output are dead. It is possible to boot from the nvme ssd in this configuration. When the GT710 is pluged in, it is no longer possible to boot from the nvme ssd. (Read Error) ---Files-------------------------------- p5ql-em.config (17 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Supermicro X10SLM-F / Gerrit and how to contribute
by Andreas Bauer Sept. 7, 2021

Sept. 7, 2021

Dear all, the other day I sucessfully flashed a X10SLM-F board to recent coreboot, and discovered an inaccuracy in coreboot src for that board. It seems that the original board support was developped on a X10SLM+-F which has two Intel I120-AT network chips. The board I flashed on the other hand is called X10SLM-F (missing the +) and has one I210 and one I217 network chip. To correct the error, I created a variant directory and overrode the devicetree.cb with the correct configuration for the board. Then I had a look at https://doc.coreboot.org/getting_started/gerrit_guidelines.html and now wonder how I can contribute a patch via Gerrit? I do not have any OpenID nor do I wish to use any commercial entity. Note that I am also in the process to divest all my data from Google, so I would prefer to not to use the parts of my Google account still left. Is there a way to contribute to Coreboot Gerrit in a privacy friendly manner using just an email address and not having my data shared with any commercial entity? Thanks, Andreas

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New Kabylake-U Laptop (Acer Aspire F5-573)
by Andreas Bauer Sept. 7, 2021

Sept. 7, 2021

Dear all, The Acer Aspire F5-573G is a low-cost laptop of the Kabylake-U platform with 6th gen i7-7500U CPU and Intel IGD 620. Stock it comes with an Insidesys H2O BIOS on a Macronix 64Mbit flash, which can be programmed in place with lastest flashrom. While low-cost in many aspects (including a really cheap display), one of the things I really like about the laptop is it's spectacular low power-consumption. It can idle at around 4.2W in a desktop environment with Wifi enabled and display at indoor brightness and go down to 2.3W at minimum brightness with Wifi disabled. I have made initial attempts to run the latest coreboot instead of the vendor bios, and based my attempts on similar Kabylake platforms. This is how far I got: | coreboot-4.14-1637-g51d0be751c-test6 Sat Sep 4 05:41:24 UTC 2021 romstage starting (log level: 8)... | pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 | gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 | gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 | gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 | gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 | TCO_STS: 0000 0000 | GEN_PMCON: d0040000 0000700a | GBLRST_CAUSE: 00000000 00000000 | prev_sleep_state 5 | FMAP: area COREBOOT found @ 630200 (1900032 bytes) | CBFS: Found 'fspm.bin' @0x9adc0 size 0x63000 in mcache @0xfef05080 | FMAP: area RW_MRC_CACHE found @ 620000 (65536 bytes) | MRC: no data in 'RW_MRC_CACHE' | bootmode is set to: 0 | SPD @ 0x52 | SPD: module type is DDR4 | SPD: module part number is | SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb | SPD: device width 16 bits, bus width 64 bits | SPD: module size is 4096 MB (per channel) | FspMemoryInit returned 0x80000007 | FspMemoryInit returned an error! | XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Here is romstage.c which I mostly copied from similar platforms and changed the I2C address of the SPD: | void mainboard_memory_init_params(FSPM_UPD *mupd) | { | const u16 rcomp_resistors[3] = { 121, 81, 100 }; | | const u16 rcomp_targets[5] = { 100, 40, 20, 20, 26 }; | | FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; | | struct spd_block blk = { | .addr_map = { 0x52 } | }; | | assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); | assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); | | get_spd_smbus(&blk); | dump_spd_info(&blk); | assert(blk.spd_array[0][0] != 0); | | memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); | memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); | | mem_cfg->DqPinsInterleaved = TRUE; | mem_cfg->MemorySpdDataLen = blk.len; | mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; | } The DIMM is an A-DATA AM1P24HC4U1-B9RS. What could be the reason for the 0x80000007 (EFI_ERROR ?) return from FspMemoryInit()? If any other parameters are missing, how do you go to extract them from the vendor bios? Andreas

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Which Mainboard for a gaming PC? Recommendations
by Paul Gerdes Sept. 6, 2021

Sept. 6, 2021

Hi I am looking for a coreboot supported Mainboard for a midrange gaming PC. I would use it mostly for gaming with Steam on Linux, some Photo editing and work. Which Boards would you recommend for this? And how is your experience with gaming on a corebooted PC? Thanks a lot! P.G.

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