We are pleased to announce that the FSP External Architecture Specification v2.3 has been posted to https://www.intel.com/fsp!
* FSP_NON_VOLATILE_STORAGE_HOB2 – A new architectural HOB has been added for storage of MRC training data. While this HOB serves the same purpose as the original FSP_NON_VOLATILE_STORAGE_HOB, it allows >64KB of MRC training data to be stored. Some of Intel’s upcoming designs will require the storage of >64KB of MRC training data, so this addition is being made in advance. Bootloaders should practice defensive programming and first search for FSP_NON_VOLATILE_STORAGE_HOB2, and only search for FSP_NON_VOLATILE_STORAGE_HOB if the former is not found in the HOB list. This algorithm will guarantee compatibility with all FSP 2.x specification versions. * FSP Version Numbers – A new ExtendedImageRevision field has been added to the FSP_INFO_HEADER. This expands the size of the Revision and Build Number fields of the FSP version number from 8 bits to 16 bits. This is done by adding a high-order byte to each of those fields. If the ExtendedImageRevision field is present, then the FSP version number is decoded as follows:
Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0] Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
Minor Version = ImageRevision[23:16]
Major Version = ImageRevision[31:24]
Both Meteor Lake and Sapphire Rapids will require storage of >64KB of MRC training data. Therefore, we recommend that bootloaders plan to have support for FSP 2.3 ready by early next year.
Does Anything Need to Change in coreboot?
Supporting future Intel SoCs will require some changes. At a minimum, coreboot will need to be modified to support the new FSP_NON_VOLATILE_STORAGE_HOB2. Additionally, it is recommended that coreboot be modified to include the ExtendedImageRevision field when printing the FSP version number. This is not strictly required from a functional standpoint, but without it the FSP version number in the boot log will not be accurate.