coreboot November 2018

coreboot@coreboot.org

71 participants
149 discussions

Re: [coreboot] Skylake (XHCI): System self start just after suspend S3.
by Naresh G. Solanki 27 Nov '18

27 Nov '18

Hi Jose, You mean connecting device to USB3 cause wake immediately after S3 entry? Can you provide kernel logs What device are you using? Does behaviour changes if different device on USB3 is used ? Also can you provided MMIO dump of PORTSC before & after S3 entry. XHCI MMIO base can be found using command: lspci -s 00:14.0 -vvvk # I guess bus 0, device 0x14, func 0 is XHCI ctrl. region 0 is MMIO base PORTSC for USB3 is in offset range 0x500-0x580. Regards, Naresh G Solanki On Tue, Nov 27, 2018 at 5:17 PM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: > > Dear coreboot engineers: > > My Skylake system S3 suspension fails because it wakes up immediately. > > If I connect the keyboard and mouse to USB2 ports and remove all USB devices from the USB3 ports then USB wake up works correctly until I connect something in the USB3 ports. > If I disable XHCI as wake up source in linux can go to S3 state but USB wake up no longer works. > > Could it be missing configuration / ASL code?... a bug? > Do somebody knows how to make it work correctly? > Thank you, > Jose Trujillo. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot -- Best regards, Naresh G. Solanki

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Re: [coreboot] Asus Chromebox Panther: no HW RNG?
by Matt DeVillier 27 Nov '18

27 Nov '18

On Tue, Nov 27, 2018 at 1:15 AM Grant Grundler <span> wrote: > > Hi! > Asus Chromebox (Panther) with Celeron 2995U processor is supposed to > have a HW Random Number Generator: > https://ark.intel.com/products/75608/Intel-Celeron-Processor-2955U-2M-Cache… > > (Intel calls it Secure Key) > > But "modprobe intel-rng" is failing with "No such device" (Debian > 4.18.0-2-amd64 kernel). > > That's because there isn't one listed in "lspci" output: > root@stoke:~# lspci -n > 00:00.0 0600: 8086:0a04 (rev 09) > 00:02.0 0300: 8086:0a06 (rev 09) > 00:03.0 0403: 8086:0a0c (rev 09) > 00:14.0 0c03: 8086:9c31 (rev 04) > 00:16.0 0780: 8086:9c3a (rev 04) > 00:1b.0 0403: 8086:9c20 (rev 04) > 00:1c.0 0604: 8086:9c14 (rev e4) > 00:1c.1 0604: 8086:9c16 (rev e4) > 00:1c.2 0604: 8086:9c18 (rev e4) > 00:1f.0 0601: 8086:9c45 (rev 04) > 00:1f.2 0106: 8086:9c03 (rev 04) > 00:1f.3 0c05: 8086:9c22 (rev 04) > 00:1f.6 1180: 8086:9c24 (rev 04) > 01:00.0 0200: 10ec:8168 (rev 0c) > 02:00.0 0280: 168c:0034 (rev 01) > > Could Firmware add the HW RNG so intel-rng is happy? > > (I'll append human readable below) > > Current firmware is: > [ 0.000000] DMI: Google Panther/Panther, BIOS MattDevo 04/18/2016 > > And if this is fixed in a newer firmware update, please hand me the > paper bag I can hide under. :) I've downloaded a newer version of the > SeaBIOS but haven't (yet) found the instructions to install it. While not likely to fix your issue, that firmware is very old, and updating wouldn't be a terrible idea. You can update via my ChromeOS Device Firmware Utility Script, see https://mrchromebox.tech/#fwscript. Both UEFI and Legacy Boot (SeaBIOS) versions are available for your device. > > Why do I care about HW RNG? > Because of this: > ... > [ 8.560270] r8169 0000:01:00.0 enp1s0: link up > [ 8.560287] IPv6: ADDRCONF(NETDEV_CHANGE): enp1s0: link becomes ready > [19039.712644] random: crng init done > [19039.712649] random: 7 urandom warning(s) missed due to ratelimiting > [19044.485625] wlp2s0: authenticate with ... > ... I'm surprised you're seeing this with such a recent kernel. I saw this on a few Chromebooks with earlier 4.1x kernels, and would manifest as a delay in the desktop loading, but could be mitigated by providing trackpad input. A quick googling says to install the rng-tools5 package if you haven't already > > Yes, several *hours* until the crng was initialized and then > wpa_supplicant could start talking on WIFI. :( > > The length of the delay varies...shortest was 7 minutes. > > thanks for any help, > grant > > > # lspci > 00:00.0 Host bridge: Intel Corporation Haswell-ULT DRAM Controller (rev 09) > 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT > Integrated Graphics Controller (rev 09) > 00:03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09) > 00:14.0 USB controller: Intel Corporation 8 Series USB xHCI HC (rev 04) > 00:16.0 Communication controller: Intel Corporation 8 Series HECI #0 (rev 04) > 00:1b.0 Audio device: Intel Corporation 8 Series HD Audio Controller (rev 04) > 00:1c.0 PCI bridge: Intel Corporation 8 Series PCI Express Root Port 3 (rev e4) > 00:1c.1 PCI bridge: Intel Corporation 8 Series PCI Express Root Port 4 (rev e4) > 00:1c.2 PCI bridge: Intel Corporation 8 Series PCI Express Root Port 5 (rev e4) > 00:1f.0 ISA bridge: Intel Corporation 8 Series LPC Controller (rev 04) > 00:1f.2 SATA controller: Intel Corporation 8 Series SATA Controller 1 > [AHCI mode] (rev 04) > 00:1f.3 SMBus: Intel Corporation 8 Series SMBus Controller (rev 04) > 00:1f.6 Signal processing controller: Intel Corporation 8 Series > Thermal (rev 04) > 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. > RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c) > 02:00.0 Network controller: Qualcomm Atheros AR9462 Wireless Network > Adapter (rev 01) > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot</span>

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Skylake (XHCI): System self start just after suspend S3.
by Jose Trujillo 27 Nov '18

27 Nov '18

Dear coreboot engineers: My Skylake system S3 suspension fails because it wakes up immediately. If I connect the keyboard and mouse to USB2 ports and remove all USB devices from the USB3 ports then USB wake up works correctly until I connect something in the USB3 ports. If I disable XHCI as wake up source in linux can go to S3 state but USB wake up no longer works. Could it be missing configuration / ASL code?... a bug? Do somebody knows how to make it work correctly? Thank you, Jose Trujillo.

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Re: [coreboot] Supported Motherboards
by Patrick Georgi 26 Nov '18

26 Nov '18

Am Mo., 26. Nov. 2018 um 11:32 Uhr schrieb Patrick Georgi < pgeorgi(a)google.com>: > Am So., 25. Nov. 2018 um 17:14 Uhr schrieb Taiidan(a)gmx.com < > Taiidan(a)gmx.com>: > >> You're referring to the dependencies for crossgcc? >> > That's a good point, I'll see that I'll set up a mirror for those. > See https://coreboot.org/releases/crossgcc-sources/ It covers all sources required for releases since coreboot-4.0, plus everything in between starting from when buildgcc got the --urls option. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Asus KGPE-D16 with latest coreboot errors with Unsupported Hardware on Qubes 4 install missing IOMMU?
by petecb 26 Nov '18

26 Nov '18

Hi, I have an Asus KGPE-D16 motherboard I am trying to get working with Coreboot and use with Qubes 4. It has a single AMD 6386 CPU and 128Gb DDR3 ECC RAM. I have successfully cloned the git repository and built the coreboot.rom. However when I flash it on to the board and then run the Qubes installer it complains that there is an “Unsupported Hardware Error” and I get the text "This hardware lack features requred by Qubes OS. Missing features: IOMMU/VT-d/AMD-Vi , Interrupt Remapping” If I install Fedora and run dmesg, AMD-Vi and the IOMMU all appear to be fine. I have tried flashing the board with an older version of Libreboot and can confim this proceeds through the Qubes 4 installation without issue. However, I wish to use a recent version of Coreboot for support of a Pci-E SSD and to ensure I am running the latest microcode updates. Can anyone offer me some guidance please? Is it possible I am not selecting the right options when I do “make nconfig” before building the rom? Kind regards, Pete

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Re: [coreboot] Hardware needed for flashing a T530
by Peter Stuge 26 Nov '18

26 Nov '18

Mike Banon wrote: > CH341A is made by Jiangsu QinHeng Ltd., and there's a datasheet - > http://www.anok.ceti.pl/download/ch341ds1.pdf - according to which > this CH341A has just a few config registers, no internal memory for > any firmware It's a USB device; if you look at the USB protocol you'll quickly realise that it's quite likely that every single USB device runs firmware - you just never see it with some devices. > > Peter Stuge wrote: > > You can't possibly be equating Broadcom to TI in terms of openness? > > Indeed TI is more open than Broadcom, but still not completely open. Please be (much!!) more specific about how AM335x is "not completely open". You didn't answer whether you have looked at spruh73. > I don't know any single board computer that has been endorsed by Free > Software Foundation, Is that your primary metric, or do you rather try to find facts yourself? //Peter

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Re: [coreboot] Supported Motherboards
by Piotr Kubaj 26 Nov '18

26 Nov '18

@Nico By removing open-source AGESA and all boards that use them, you would remove many boards that can boot blobless (like KGPE-D16 and KCMA-D8, there's also cheap low-end like E350M1, although I'm not sure this uses AGESA). This would mean that if we want blobless, we can either use much less powerful than ASUS boards Intel-based boards from 10 years ago or use Chromebooks. This would severely lower the number of coreboot users. You said we could maintain AGESA code on our own and even rewrite. I'm with Mike about this. I'm not a firmware engineer, I can understand so-so what the code is doing but writing it is completely beyond me. I'm also engaged in other open-source project (I contribute to FreeBSD ports) and this doesn't leave time to work on coreboot. Also, running tokei in AGESA dir currently shows: pkubaj@KGPE-D16:$~/coreboot/src/vendorcode/amd/agesa/f15tn$ tokei ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Language Files Lines Code Comments Blanks ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Assembly 1 209 184 0 25 C 457 143870 77558 54737 11575 C Header 251 130554 91038 29652 9864 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Total 709 274633 168780 84389 21464 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The size of AGESA is currently about 10% of coreboot. Nico, do you think a single person working in spare time can reimplement 10% of coreboot?

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Supported Mainboard in coreboot is missing because of using LATE_CBMEM_INIT
by j443i8＠goat.si 26 Nov '18

26 Nov '18

Hello. I got a MSI MS6178 mainboard for coreboot based on the official wiki page https://www.coreboot.org/Board:msi/ms6178 I have followed the wiki to build coreboot but the board is missing in make menuconfig here: https://www.coreboot.org/Build_HOWTO Then i find https://review.coreboot.org/c/coreboot/+/23300 Thus i run 'git checkout tags/4.7' But when trying to build a image i got following error: Cloning into 'seabios'... fatal: https://review.coreboot.org/p/seabios.git/info/refs not valid: is this a git repository? Makefile:18: recipe for target 'seabios' failed Could someone fix the MSI MS6178 mainboard so that it can be used with the recent coreboot? Thanks!

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riscv: how to running coreboot on HiFive Unleashed?
by 王翔 25 Nov '18

25 Nov '18

I try to running coreboot on HiFive Unleashed, but nothing come from uart. I tested by the following steps: 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. 2. Change MSEL to 11 and boot linux 3. Copy coreboot.rom via scp 4. Write coreboot.rom to /dev/mtd0 by flashcp. 5. Change MSEL to 15 and boot coreboot. No response on uart. Do you have any suggestions? ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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Coreboots Board Status have privacy issues for contributors
by j443i8＠goat.si 25 Nov '18

25 Nov '18

I took a look into https://review.coreboot.org/cgit/board-status.git? The commit here https://review.coreboot.org/cgit/board-status.git/commit/?id=72945dee4c60b9… tells me for example that the MAC address from Paul Menzel is bc:5f:f4:c8:d3:98 . The mac address from the WLAN Router Patrick Georgi is using is based on this commit https://review.coreboot.org/cgit/board-status.git/commit/?id=addd59d8fb55dc… the mac 70:3a:cb:bd:fd:e3 . This is probably some Google device his device is connecting to because the mac range is registered to Google Inc. Now i can lookup in public wifi databases and in some cases i then know where the users lives. The mac address from Chris Thompson is 6c:f0:49:47:22:4d based on https://review.coreboot.org/cgit/board-status.git/commit/?id=da41a5a88bebc9… And the mac address from Denis 'GNUtoo' Carikli who is using parabola as os was using a Hitachi HDP725050GLA360 with firmware GM4OA52A and a second WDC WD5000AAKB-00YSA0 with firmware 12.01C02 and have switched now to a ST9160314AS with 0002SDM1 firmware. His mac address of one of his computers is bc:5f:f4:9c:b7:32 . In this computer he is using a KINGSTON SV300S37A240G with firmware 603ABBF0 . I was thinking of contributing to the Board Status but i dont want to release any private data and wont contribute now. What is the usage of the world to know what mac address the people are using? Please fix this to: 1) Remove kernel log and replace it with "uname -r" to just know the kernel version. 2) Please make the contribution without the force of having to register to git. Make a public account that have just access to the board-status.git and set this public account into the code itself. Then there can be for example a simple live linux iso that people can boot with LAN cable connected. No requirement of installation software, of setting things up or anything like that.

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coreboot November 2018