coreboot October 2018

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145 discussions

Re: [coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Jose Trujillo 31 Oct '18

31 Oct '18

Lance: I followed your advice and fetched coreboot master today and now entered into the payload domain "0xF8".... Still have problems because tianocore does not load the operating system and other issues but this is another story for tomorrow. Thank you, Jose. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Wednesday, October 31, 2018 4:08 AM, Lance Zhao <lance.zhao(a)gmail.com> wrote: > Feels like CoffeeLake RVP11 still been actively uploaded with newer changes. But at least your coreboot code seems to be outdated, all of those coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently. I will suggest you to sync up your code base and try again. > > Lance > > On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: > >> Hello coreboot engineers: >> >> I am using the "coffeelake RVP11" to test the code on my "non RVP" system. >> The payload doesn't load. >> >> I found several errors in the attached log: >> >> 1.- Device ID's of the system are still not existant in coreboot. >> 2.- Misconfigured # of MAX CPU CORES. >> 3.- Maybe memory is still not properly initialized because RVP platform uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD channel. >> >> Please help me to identify the root of the problem that causes RAM "Failed Segment".... >> Thank you in advance. >> Jose Trujillo. >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Jose Trujillo 31 Oct '18

31 Oct '18

XIP was already selected, the FSP headers updated and the right platform chosen... so, i didn't know what to do, that was the reason I decided to test on previous version. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Wednesday, October 31, 2018 9:13 AM, Lance Zhao <lance.zhao(a)gmail.com> wrote: > The "Invalid FSPM signature" at this stage, if FspUpd.h for coffeelake already there. maybe "XIP mode" had not been selected in config file? > > On Tue, Oct 30, 2018 at 10:42 PM Jose Trujillo <ce.autom(a)protonmail.com> wrote: > >> Thank you Lance; >> >> I got back to 4.8.1 because on master of 2 weeks ago I was getting post code 0x34 "Invalid FSPM signature"; but I will try again. >> Coreboot engineers have been doing much work on integrating FSP to coreboot and may be the reason has been unstable. >> >> Jose. >> >> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ >> On Wednesday, October 31, 2018 4:08 AM, Lance Zhao <lance.zhao(a)gmail.com> wrote: >> >>> Feels like CoffeeLake RVP11 still been actively uploaded with newer changes. But at least your coreboot code seems to be outdated, all of those coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently. I will suggest you to sync up your code base and try again. >>> >>> Lance >>> >>> On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: >>> >>>> Hello coreboot engineers: >>>> >>>> I am using the "coffeelake RVP11" to test the code on my "non RVP" system. >>>> The payload doesn't load. >>>> >>>> I found several errors in the attached log: >>>> >>>> 1.- Device ID's of the system are still not existant in coreboot. >>>> 2.- Misconfigured # of MAX CPU CORES. >>>> 3.- Maybe memory is still not properly initialized because RVP platform uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD channel. >>>> >>>> Please help me to identify the root of the problem that causes RAM "Failed Segment".... >>>> Thank you in advance. >>>> Jose Trujillo. >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Lance Zhao 31 Oct '18

31 Oct '18

The "Invalid FSPM signature" at this stage, if FspUpd.h for coffeelake already there. maybe "XIP mode" had not been selected in config file? On Tue, Oct 30, 2018 at 10:42 PM Jose Trujillo <ce.autom(a)protonmail.com> wrote: > Thank you Lance; > > I got back to 4.8.1 because on master of 2 weeks ago I was getting post > code 0x34 "Invalid FSPM signature"; but I will try again. > Coreboot engineers have been doing much work on integrating FSP to > coreboot and may be the reason has been unstable. > > Jose. > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On Wednesday, October 31, 2018 4:08 AM, Lance Zhao <lance.zhao(a)gmail.com> > wrote: > > Feels like CoffeeLake RVP11 still been actively uploaded with newer > changes. But at least your coreboot code seems to be outdated, all of those > coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently. > I will suggest you to sync up your code base and try again. > > Lance > > On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot < > coreboot(a)coreboot.org> wrote: > >> Hello coreboot engineers: >> >> I am using the "coffeelake RVP11" to test the code on my "non RVP" system. >> The payload doesn't load. >> >> I found several errors in the attached log: >> >> 1.- Device ID's of the system are still not existant in coreboot. >> 2.- Misconfigured # of MAX CPU CORES. >> 3.- Maybe memory is still not properly initialized because RVP platform >> uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD >> channel. >> >> Please help me to identify the root of the problem that causes RAM >> "Failed Segment".... >> Thank you in advance. >> Jose Trujillo. >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Jose Trujillo 31 Oct '18

31 Oct '18

Thank you Lance; I got back to 4.8.1 because on master of 2 weeks ago I was getting post code 0x34 "Invalid FSPM signature"; but I will try again. Coreboot engineers have been doing much work on integrating FSP to coreboot and may be the reason has been unstable. Jose. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Wednesday, October 31, 2018 4:08 AM, Lance Zhao <lance.zhao(a)gmail.com> wrote: > Feels like CoffeeLake RVP11 still been actively uploaded with newer changes. But at least your coreboot code seems to be outdated, all of those coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently. I will suggest you to sync up your code base and try again. > > Lance > > On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot <coreboot(a)coreboot.org> wrote: > >> Hello coreboot engineers: >> >> I am using the "coffeelake RVP11" to test the code on my "non RVP" system. >> The payload doesn't load. >> >> I found several errors in the attached log: >> >> 1.- Device ID's of the system are still not existant in coreboot. >> 2.- Misconfigured # of MAX CPU CORES. >> 3.- Maybe memory is still not properly initialized because RVP platform uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD channel. >> >> Please help me to identify the root of the problem that causes RAM "Failed Segment".... >> Thank you in advance. >> Jose Trujillo. >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Lance Zhao 31 Oct '18

31 Oct '18

Feels like CoffeeLake RVP11 still been actively uploaded with newer changes. But at least your coreboot code seems to be outdated, all of those coffeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently. I will suggest you to sync up your code base and try again. Lance On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot < coreboot(a)coreboot.org> wrote: > Hello coreboot engineers: > > I am using the "coffeelake RVP11" to test the code on my "non RVP" system. > The payload doesn't load. > > I found several errors in the attached log: > > 1.- Device ID's of the system are still not existant in coreboot. > 2.- Misconfigured # of MAX CPU CORES. > 3.- Maybe memory is still not properly initialized because RVP platform > uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD > channel. > > Please help me to identify the root of the problem that causes RAM "Failed > Segment".... > Thank you in advance. > Jose Trujillo. > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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CoffeeLake RVP11: Post code 0x7A "SELF Payload doesn't target RAM:
by Jose Trujillo 30 Oct '18

30 Oct '18

Hello coreboot engineers: I am using the "coffeelake RVP11" to test the code on my "non RVP" system. The payload doesn't load. I found several errors in the attached log: 1.- Device ID's of the system are still not existant in coreboot. 2.- Misconfigured # of MAX CPU CORES. 3.- Maybe memory is still not properly initialized because RVP platform uses LPDDR4 and use SPD.bin VS my system that use DDR4 SO-UDIMM on SMB SPD channel. Please help me to identify the root of the problem that causes RAM "Failed Segment".... Thank you in advance. Jose Trujillo.

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Re: [coreboot] Reducing FSP performance time
by Nico Huber 30 Oct '18

30 Oct '18

> We are new to this. Can you please share some sample code which skips this FSP temp RAM function ? It should be an option in the Chipset menu. What it's called and what choices you have depends on your platform. Nico -- Sent from my Android device with K-9 Mail. Please excuse my brevity.

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Re: [coreboot] Reducing FSP performance time
by Nico Huber 30 Oct '18

30 Oct '18

Hi Antony, On 10/26/18 6:50 AM, Antony AbeePrakash X V wrote: > ID:952 - 953 is FSP_TEMP_RAM_EXIT which takes around 1.7 sec. Below are the queries: FSP's temp-ram function is redundant with proper coreboot code. I can only advice against using an FSP function if an open-source version exists. With the open-source path you'd have much more insight in what happens. Maybe switching to the native coreboot code already helps reducing the delay. Nico

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Re: [coreboot] Matrix instead (or additionally to) IRC
by Timothy Pearson 29 Oct '18

29 Oct '18

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 On 10/28/2018 02:41 PM, Patrick Georgi via coreboot wrote: > Not sure if that is still working > but https://matrix.org/blog/2015/06/22/the-matrix-org-irc-bridge-now-bridges-al… > should help connect to IRC via matrix. > > Choose your own protocol ;-) More importantly, choose your own application. There are so many good choices for desktop-side IRC clients at this point that almost certainly any older developers have already settled on one. Forcing us to switch clients, or keep a browser tab open, will just shut down the real time channel and make Email seem like the most attractive option. ;-) - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBCAAGBQJb1i33AAoJEK+E3vEXDOFb8sQH/0py9i68f0s+ZT25TK1x/G9i kGnHNTi/lZGcBu8BhTxRq9NTUildaljC/eAMDcLFP7vwalSsPgQnGIXxZfxwj4I5 keNffwSl68Rt2E0tLhFnwp9J7hmznri6+wemPK8px6lWqKlbsUBCrcZ2d1QWDHDT Cjtl1h21/bKkK8LDtSvl+5zRon4EFrg1cGIx1wRtDsRTnl05IOSMuyQqWueqdbxy Hc3rcZI/rh0RpmtbDORtu0smpW3n3EFIwBpADDqNQZG4A44Qh/p2GtuBhQV9kVan 4hxdtJe+iS6vVsFHxCfhqVf4OVrdDYq8FFT+DTBl4NbpY8sLYHlqefnqiWC5o7A= =lLHJ -----END PGP SIGNATURE-----

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Re: [coreboot] Matrix instead (or additionally to) IRC
by Duncan Guthrie 29 Oct '18

29 Oct '18

You can register your Matrix nickname on Freenode. There is apparently such an option. So, it still should work. On 29/10/2018 00:35, Iru Cai wrote: > Previously it works, but now #coreboot needs registered nicks. > > On Mon, Oct 29, 2018 at 3:43 AM Patrick Georgi via coreboot < > coreboot(a)coreboot.org> wrote: > >> Not sure if that is still working but >> https://matrix.org/blog/2015/06/22/the-matrix-org-irc-bridge-now-bridges-al… >> should help connect to IRC via matrix. >> >> Choose your own protocol ;-) >> >> Am So., 28. Okt. 2018, 15:11 hat Philipp Stanner <stanner(a)posteo.de> >> geschrieben: >> >>> Hey, >>> >>> have you guys already heard of Matrix? >>> https://matrix.org/blog/home/ >>> >>> It's some sort of modern IRC, using JSON to format messages. It's more >>> modern than IRC. Features are: >>> * Source code formatting and highlighting in messages >>> * multiple devices >>> * history + history synchronization between multiple devices >>> * possible E2C encryption >>> >>> and many more. >>> In theory it will be a decentralized protocol, but there aren't that >>> many servers yet and actually only one working server-software >>> >>> Many projects, especially tech-based ones like the Rust programming >>> language already use the service. >>> >>> Personally I think it's an enormous progress to IRC. I would give it a >>> chance if I were you :) >>> >>> P. >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://mail.coreboot.org/mailman/listinfo/coreboot >>> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > > >

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coreboot October 2018