coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

Re: [coreboot] Passing CFLAGS to coreboot make (and reproducible builds)
by Trammell Hudson 02 Feb '17

02 Feb '17

On Thu, Feb 02, 2017 at 08:55:56PM +0100, Zoran Stojsavljevic wrote: > > Is there a right way to pass additional compiler flags to the coreboot > > makefiles? We've been working on making the Heads firmware reproducible > > and found that the -fdebug-prefix-map option is necessary to deal with > > different build directories. To make this work with coreboot we ended > > passing in environment variables CFLAGS_x86_32 and *CFLAGS_x86_64*: > > In other words, Trammel, you would like to say that you can compile > Coreboot to be x86_64 compliant (64 bits Coreboot build)?! Or more likely I saw both of them in the Makefile and just passed in both of them for good measure, but didn't go back to check which ones were actually required for a qemu/x230/chell mainboard build... -- Trammell

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Passing CFLAGS to coreboot make (and reproducible builds)
by Trammell Hudson 02 Feb '17

02 Feb '17

Is there a right way to pass additional compiler flags to the coreboot makefiles? We've been working on making the Heads firmware reproducible and found that the -fdebug-prefix-map option is necessary to deal with different build directories. To make this work with coreboot we ended passing in environment variables CFLAGS_x86_32 and CFLAGS_x86_64: EXTRA_FLAGS="-fdebug-prefix-map=`pwd`=. -gno-record-gcc-switches" make CFLAGS_x86_32="$EXTRA_FLAGS" CFLAGS_x86_64="$EXTRA_FLAGS" Ideally coreboot could use this in its Makefile to avoid having any build tree path dependencies included in the binary, although for now the Heads build script passes in these extra flags to all of our dependencies. With this (and several other commits this week), Heads is now 100% reproducible (tested on Ubuntu, Qubes' Fedora, and an ancient Debian): https://github.com/osresearch/heads/releases/tag/v0.1.0 -- Trammell

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Re: [coreboot] Back to original BIOS
by Peter Stuge 02 Feb '17

02 Feb '17

Michal Widlok wrote: > Ron - I've lost original bios, my mistake. I think that will be a problem. Lenovo BIOSes save some machine-specific information in the flash ROM across updates, and I've so far not seen a single Lenovo mainboard which does not require this information for the vendor BIOS to work. > On Wed, Feb 1, 2017 at 9:20 PM, Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> wrote: > > I'll try to find the original BIOS for Michael It's a kind offer, but not useful in my experience, for the above reasons. All Lenovo BIOS updates I've seen so far require a Lenovo BIOS. //Peter

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2017 North American coreboot Conference
by Martin Roth 02 Feb '17

02 Feb '17

We are happy to announce that the 2017 North American coreboot Conference will be held in Denver, Colorado on June 5th & 6th, with an optional hacking day on June 7th. Register here: https://goo.gl/o2j4gX The cost will be $250 for corporate attendees, $100 for individuals, and $25 for students. All fees go up by $50 for registrations received after May 5. Payment is NOT required at the time of registration. We will contact you later with payment information. Hotel, travel, and other additional information is available on the coreboot wiki: https://www.coreboot.org/Denver2017 If you have any questions, please email us at convention(a)coreboot.org Martin

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Zoran Stojsavljevic 02 Feb '17

02 Feb '17

> As for our prototype, we got it to boot with one memory channel while ‘hot’. We’re working with Intel to narrow it down, > but it looks like a marginal trace length issue. The verbose FSP tells us we are having issues during Command Clock Training. As I recall, INTEL provides HW PCB evaluation support for custom platforms, for VIP IOTG customers. There is also INTEL trace length calculation tool, for each family of ATOM/CORE. Important things to note (area: board HW design and verification), Andy. [image: Inline image 1] Since I also recall that Rangeley has some Gen.3 SATA support (2 ports), I also will advise you to check/pay attention to these, during Lane Clock training/SATA 3 Protocol training... Just in case. Good Luck, Zoran On Thu, Feb 2, 2017 at 2:28 PM, Andy Knowles <aknowles(a)galleonec.com> wrote: > A follow-up, for posterity: > > > > I got the RCC-DFF from ADI to boot using the memory down option. To do > this, I enabled Memory Down in the FSP (via BCT) and also changed all of > the SPD SMBus Addresses to 0xff, to make sure the EEPROM wasn’t being > used. Booting with this FSP I get an expected “No DIMMs Present” error. > > > > I then modified src/mainboard/adi/rcc-dff/romstage.c as attached, > specifying the SPD data from the Kingston datasheet and one populated DIMM > on channel 0. > > > > The RCC-DFF then booted normally. > > > > As for our prototype, we got it to boot with one memory channel while > ‘hot’. We’re working with Intel to narrow it down, but it looks like a > marginal trace length issue. The verbose FSP tells us we are having issues > during Command Clock Training. > > > > Thanks again for responses! > > > > Andy > > > > > > *From:* coreboot [mailto:coreboot-bounces@coreboot.org] *On Behalf Of *Andy > Knowles > *Sent:* Monday, 23 January 2017 11:55 > *To:* Agrain Patrick <patrick.agrain(a)al-enterprise.com> > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value > exceeds limits" during memory init > > > > This sender failed our fraud detection checks and may not > be who they appear to be. Learn about spoofing > <http://aka.ms/LearnAboutSpoofing> > > Feedback <http://aka.ms/SafetyTipsFeedback> > > Hi Patrick, > > > > I have an RCC-DFF from ADI. The memory is soldered down, but from their > BIOS source it seems they aren’t using the FSP memory down option, so I > suspect they have an EEPROM on the board with SPD data pretending to be a > DIMM. I’m going to try booting it with memory down set in FSP and SPD data > in coreboot instead. > > > > Thanks, > > Andy > > > > *From:* Agrain Patrick [mailto:patrick.agrain@al-enterprise.com > <patrick.agrain(a)al-enterprise.com>] > > HI Andy, > > > > RCC-VE dev board from ADI has also memory down. It may help to compare. > But unfortunately, schematics are not available. > > Regards, > > Patrick Agrain > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 02 Feb '17

02 Feb '17

The ASUS KGPE-D16 fails verification for branch master as of commit 3236f7be093b3dfed606d6a6b4e81743ecfe0c5c The following tests failed: BOOT_FAILURE Commits since last successful test: 3236f7b ectool: Support OpenBSD See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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USB problems in Haswell+Lynxpoint motherboards
by Аладышев Константин 02 Feb '17

02 Feb '17

Does someone have moherboards with Haswell+Lynxpoint? I have problems with USB. In Linux USB devices work fine with "ehci-pci" driver and don't work correctly with "ehci-hcd" driver (they freeze completely short time after boot). In Windows USB devices work fine in safe mode and don't work correctly with normal mode (again they freeze completely short time after boot). What is the difference between these two Linux drivers and what can be the source of this problem?

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Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init
by Andy Knowles 02 Feb '17

02 Feb '17

A follow-up, for posterity: I got the RCC-DFF from ADI to boot using the memory down option. To do this, I enabled Memory Down in the FSP (via BCT) and also changed all of the SPD SMBus Addresses to 0xff, to make sure the EEPROM wasn’t being used. Booting with this FSP I get an expected “No DIMMs Present” error. I then modified src/mainboard/adi/rcc-dff/romstage.c as attached, specifying the SPD data from the Kingston datasheet and one populated DIMM on channel 0. The RCC-DFF then booted normally. As for our prototype, we got it to boot with one memory channel while ‘hot’. We’re working with Intel to narrow it down, but it looks like a marginal trace length issue. The verbose FSP tells us we are having issues during Command Clock Training. Thanks again for responses! Andy From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of Andy Knowles Sent: Monday, 23 January 2017 11:55 To: Agrain Patrick <patrick.agrain(a)al-enterprise.com> Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value exceeds limits" during memory init This sender failed our fraud detection checks and may not be who they appear to be. Learn about spoofing<http://aka.ms/LearnAboutSpoofing> Feedback<http://aka.ms/SafetyTipsFeedback> Hi Patrick, I have an RCC-DFF from ADI. The memory is soldered down, but from their BIOS source it seems they aren’t using the FSP memory down option, so I suspect they have an EEPROM on the board with SPD data pretending to be a DIMM. I’m going to try booting it with memory down set in FSP and SPD data in coreboot instead. Thanks, Andy From: Agrain Patrick [mailto:patrick.agrain@al-enterprise.com] HI Andy, RCC-VE dev board from ADI has also memory down. It may help to compare. But unfortunately, schematics are not available. Regards, Patrick Agrain

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Re: [coreboot] Back to original BIOS
by Zoran Stojsavljevic 02 Feb '17

02 Feb '17

Hello Michael, As promised (and I ALWAYS keep my promises): Drivers for various WIN OSes: http://www.driverscape.com/manufacturers/lenovo/laptops-desktops/ http://www.driverscape.com/manufacturers/lenovo/laptops-desktops/27672mg/36… BIOS upgrade for WIN7: http://support.lenovo.com/de/en/products/Laptops-and-netbooks/ThinkPad-T-Se… As my understanding is, you should put some blank HDD, install using Coreboot with SeaBIOS payload (*emulating legacy BIOS*) WIN7 (32 or 64), and then download .iso with latest BIOS update/upgrade for T400 here, then make* legacy USB .iso bootable CD/DVD or USB*: http://support.lenovo.com/de/en/products/laptops-and-netbooks/thinkpad-t-se… Please, report back here the results! Thank you, Zoran On Wed, Feb 1, 2017 at 9:50 PM, Michal Widlok <michalwd1979(a)gmail.com> wrote: > Thank You for quick reply. > Ron - I've lost original bios, my mistake. I hoped nobody would ask > and spare me saying "I'm a moron" :-). > Zoran - This is TYPE 2767-2MG S/N R80DCTZ6 09/09. The one with > "switchable graphics" (Intel and Ati) onboard. Is any more info > required? Anyway since lenovo provides single update for every T400 > model then it might not matter - or I am very wrong. > > Michael Widlok > > On Wed, Feb 1, 2017 at 9:20 PM, Zoran Stojsavljevic > <zoran.stojsavljevic(a)gmail.com> wrote: > > Hello Ron, > > > > No worries. I'll try to find the original BIOS for Michael, if Michael > gives > > me exact model of Lenovo T400. > > > > Don't you agree? ;-) > > > > Zoran > > > > On Wed, Feb 1, 2017 at 8:41 PM, ron minnich <rminnich(a)gmail.com> wrote: > >> > >> did you save the bios before you flashed it? > >> > >> On Wed, Feb 1, 2017 at 11:11 AM Michal Widlok <michalwd1979(a)gmail.com> > >> wrote: > >>> > >>> Hello, > >>> > >>> Is it possible to flash back original BIOS from coreboot system on > >>> lenovo T400? I would like to play with tp_smapi module (battery checks > >>> at most). My board is already equipped with a connector from FLASH > >>> chip to Raspberry pi, so it can be hardware or software method. > >>> > >>> I've red about bios update from bootable CD or USB stick - will this > >>> method work with coreboot? > >>> Best Regards, > >>> Michael Widlok > >>> > >>> -- > >>> coreboot mailing list: coreboot(a)coreboot.org > >>> https://www.coreboot.org/mailman/listinfo/coreboot > >> > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> https://www.coreboot.org/mailman/listinfo/coreboot > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] GRUB2 compilation failure
by Taiidan＠gmx.com 02 Feb '17

02 Feb '17

Could you provide all the commands from start to finish that you used to build coreboot with? By any chance did you make the cross toolchain? or are you compiling without it?

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coreboot February 2017