coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

How does SeaBIOS transition to Linux?
by Haleigh Novak 09 Feb '17

09 Feb '17

Hello All, I was wondering if anyone could take a few minutes and explain the proccess of how coreboots SeaBIOS payload (or even how coreboot itself) transitions into a Linux boot sequence to me? I understand that in some memory section there is an assembly command that tells the system to jump somewhere (if anyone knows where this assembly segment is I would love to know as a base for more searching) to begin the Linux boot process and after that jump Linux takes it from there; what I'm seeking in asking this question here is a detailed (the more detailed the better), if possible step by step command set on how SeaBIOS turns into Linux - or a pointer in the direction to find the actual assembly code that instructs this transition. I have been googling for approximatly two hours now and have been unable to find anything other than super general 'SeaBIOS knows how to query this thing, then that just goes here, etc'. I know this is probably something most might think is trivial and I apologise for that, but I really dont understand the transition on the level that I feel I need to so I figured I would ask the best. Thank you for your time. HN

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Re: [coreboot] Back to original BIOS
by Igor Skochinsky 09 Feb '17

09 Feb '17

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 08 Feb '17

08 Feb '17

The ASUS KGPE-D16 fails verification for branch master as of commit 0254c2d99fc7a5858be4826c576ca743d005b213 The following tests failed: BOOT_FAILURE Commits since last successful test: 0254c2d southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN 7d14af8 soc/intel/apollolake: dump CSE status See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Re: [coreboot] Back to original BIOS
by Michal Widlok 08 Feb '17

08 Feb '17

Hello Zoran, I've run quite a lot of test recently and the results are in fact inconclusive... Following is the (long) description of experiments I made recently and in the past. 1. BIOS structure. T400 Bios does not fully looks like T420. It seems that BIOS does not start at 0x500000 more likely at 0x600000 The MAC address can be find 4 or 5 times in the image at: 0x22F48, 0x81FDD, 0x5F6000, 0x5F7000. In fact it is in different places in different images, however last 2 locations 0x5F6000, 0x5F7000 are always the same. Looking around I find nice info about the bios, made by people that by-pass whitelists in lenovo bioses - You might find it interesting: http://www.endeer.cz/bios.tools/ http://www.endeer.cz/bios.tools/bios.html http://web.dodds.net/~vorlon/wiki/blog/Upgrading_a_ThinkPad_BIOS/ With phnxsplit I was able to get 60 different files out of the bios image and it seems that the tool works right. I'm attaching a list of modules the program found, description of "code characters" can be found in phnxfunc.c. This tool compiles on Linux, but it need some simple patching because of tons of compiler warnings. 2. Coreboot/libreboot. For testing I used precompiled libreboot image from https://libreboot.org/release/stable/20160907/rom/grub/ made for T400. Can be put on any machine (overwritting all flash chip) and it works equally well. MAC adresses are at 0x1000 and 0x2000 in the image and can be changed with ich9gen - I think that You know it well. 3. Moving bioses - this is strange. In the past when I just started working on T400 I had one board with already installed coreboot and one with original bios. Coreboot board had ati and intel graphics, while bios board only intel. I decided to exchange flash chips and it worked. Now it really sounds strange, but both boards booted OK and original bios correctly detected that it is on dual graphics board and show right menu options. Then after upgrading bios to the latest version (3.22) the board experienced long booting problem. It happens and there are threads on lenovo forums about it, so I assume that it nothing to do with the chip exchange. I tried to fix by changing settings of TPM chip and after enabling it the board did not boot at all - I left the board as spare parts supply then. Now I took it back and started to experiment: put the libreboot image - works right, but any other original bios image and it does not boot. On the other hand other board (with just intel graphics) works with any original bios image - I've tried 2 different, again overwritting whole chip. It seems that the problem is not related to flash chip data but maybe to RFID memory You mentioned, or TPM. I don't know what can I do about it - maybe boot the machine with coreboot and then try to change some TPM settings on Linux?? 4. Further tests. I put back 2 T400 laptops with easily accessible programming connectors, so now I can play with any images without complicated disassembly. If there is anything I can check/post/try then let mo know. My ultimate dream would be to have tp_smapi functionality in coreboot, but it seems that this is a long way ahead. Anyway I am attaching descriptor (0x0-0x1000) from original bios image. Very Best Regards, Michael Widlok On Sun, Feb 5, 2017 at 6:00 PM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > Hello Michael, > > Before doing any programming, I have here couple suggestions to you. You > should investigate. > > Namely, this: http://thinkwiki.de/UEFI_BIOS_T420_BIOS_Structure > > Also, you should look upon the movie here: https://www.youtube.com/ > watch?v=DLwaKb6pLrc&feature=player_embedded > > Since I am not sure that T420 UEFI BIOS is the same structure as legacy > BIOS T400 has (since I remember that T420 is UEFI, legacy/CSM was on - I > had one at work since 2011 till 2014). But it is worth trying, nothing to > lose. > > Knowing that T420 BIOS structure looks like (and I bet it is stored in > only one 8MB flash, as my best bet): > > [image: Inline image 1] > > You should read your T400 Coreboot flash content, and try to see if it > complies with the given above structure. If it does, you are All Cool. > Namely, you should try to read GbE region, and see where the MAC address > (which you find using Linux command: ifconfig -a). If you appear to find > the spot, you are 100% sure you are All Good, since then you'll read > another BIOS content, and after you will have lot of possibilities for > experiments: > [1] You can reprogram the BIOS from original BIOS to your Coreboot flash > rewriting last 0x300000 bytes; > [2] You can rewrite original MAC address to another BIOS, and try to boot; > [3] You can compare/combine regions, and see what'll happen?! > [4] You name it! > > I have no idea if you tampered with ME... And no idea if ME for each > LENOVO specimen keeps some unique data from/for the platform. > > But I am eager to hear/read what did you find investigating about T400 > structure, does it looks the same as T420, and et cetera. :-) > > You can also read descriptor region, and post it somewhere, so we can peek > into it (I remember, I have somewhere some explanations about some of these > descriptor region data). > > Thank you, > Zoran > > On Sat, Feb 4, 2017 at 8:41 AM, Michal Widlok <michalwd1979(a)gmail.com> > wrote: > >> Zoran, I'm working on this subject now, but I need to do regular work too >> :-). >> >> Seriously I'm in the process of changing my current stationary >> work-horse to two T400 laptops on docking stations. I've just received >> docks (very dirty, noisy fans) and I borrowed my Raspberry programmer >> to a friend. I hope to finish working on hardware this weekend and I >> will be ready to play with bioses when I get Raspberry back. I think >> that the first method would be to "copy" flash from one board to >> another and we will see. I also try to change MAC in original bios, >> maybe this is possible. I will report everything back, hope it will >> help someone. >> Michael Widlok >> >> PS. Sorry for double mail I messed addresses. >> >> On Fri, Feb 3, 2017 at 9:58 PM, Zoran Stojsavljevic >> <zoran.stojsavljevic(a)gmail.com> wrote: >> > Ron, I do agree, does not seem to be promising. It will add problems >> down >> > the road, as requirements grow. >> > >> > Zoran >> > >> > On Fri, Feb 3, 2017 at 8:45 PM, ron minnich <rminnich(a)gmail.com> wrote: >> >> >> >> >> >> >> >> On Fri, Feb 3, 2017 at 9:45 AM Zoran Stojsavljevic >> >> <zoran.stojsavljevic(a)gmail.com> wrote: >> >>> >> >>> >> >>> >> >>> Ron, any (practical) example of above described practices? I have in >> my >> >>> laptops here 6 x 4 GB DIMM modules and 2 x 8GB DIMM modules, all of >> them >> >>> have SPD mounted. >> >> >> >> >> >> >> >> DIMMs are so great but so old school :-) >> >> >> >> on some systems, in flash, there are 4 and 8 element tables which are >> >> indexed by GPIOs .You use the 2 or 3 bits from 2-3 GPIOs to index the >> table >> >> and that's how you get your RAM programming. No SPD. You can see how >> much >> >> room this leaves for problems. >> >> >> >> This is just one simple example. >> >> >> >> ron >> >> >> > >> > >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Supermicro H8QGI-F (Quad G34) - blob status?
by Taiidan＠gmx.com 07 Feb '17

07 Feb '17

https://www.coreboot.org/Board:supermicro/h8qgi A quad g34 with 1TB RAM would be nice to have... I am creating a beginners guide with all the new enough to be useful and easily available brand new in box boards, I am curious if anyone uses this as I have the following questions: - Does it work without blobs? (what happens if you don't include the video bios blob? can you still get video via seabios or linux?) - Can you de-activate the on-board iKVM? (sketchy, it seems to have an interface to one of the regular nics too) - Are there any problems with reaching the full OEM 1TB spec RAM (like where the kgpe-d16 can only go to 192gb instead of the spec'ed 256

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Re: [coreboot] Thinkpad T420 Thermal Management
by Arian Sanusi 07 Feb '17

07 Feb '17

Hi > Anybody tested Thinkpad T420's thermal management and fan speed control? I'm running one albeit with an i7-3740qm - which is too much thermal load, runs up to 2.9 GHz for me reaching 93°C (70K to ambient) with fan set to disengaged, normal auto fan control works and allows up to 2.5 GHz. with that CPU RAPL does not work, thermald does but out-of-the-box settings gives me less performance than with fix limits, and I'm sure as hell not going to configure something with an xml config file. used to have a 2720m which worked without any issues AFAIR, but the 3740qm effectively gives me double the cores that are a little faster. anything else you want to know? Best, Arian

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Thinkpad T420 Thermal Management
by ilker 07 Feb '17

07 Feb '17

Hi Anybody tested Thinkpad T420's thermal management and fan speed control?

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[PUBLIC INFO] Intel's Atom C2000 chips are bricking products – and it's not just Cisco hit
by Zoran Stojsavljevic 07 Feb '17

07 Feb '17

Intel's Atom C2000 chips are bricking products – and it's not just Cisco hit http://www.theregister.co.uk/2017/02/06/cisco_intel_decline_to_link_product… Just read it on the news. Since I have noticed that some people here use Coreboot with C2000 microservers' FSP products, they should read this article, and see if it helps them, anyhow?! The comments for this article are here... All on your own peril! https://forums.theregister.co.uk/forum/1/2017/02/06/cisco_intel_decline_to_… (and, this is the public info - please, no one should say that I am bashing INTEL, I am not) :-) Zoran

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Best supported modern laptop?
by Philipp Stanner 07 Feb '17

07 Feb '17

I'm going to buy a new laptop soon (has to have a touchscreen) and am considering buying one which supports coreboot. Which model would that be? >From what the wiki tells me The X220 is supported best, thanks to Vladimir, but also the X201 is listed in the green area. The wiki lists some noticeable issues for the X201, though. Still it's green. Are those issues (especially "The X201 immedeatly powers off after resuming from suspend resulting a completely lost session sometimes (Race condition)" still unsolved? thx

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Question about the devicetree.cb
by Maxim Gusev 06 Feb '17

06 Feb '17

Hi friends! I really hope for your help in understanding this challenge. My questions will be about the devicetree.cb file in mainboards directories. There are chips devices and registers in the tree. As I understood a chip may be made up of one or more devices. Also, some chips (for example southbridge) require configuration prior to the device configuration. There are different device types also. As it written in the https://www.coreboot.org/Creating_A_devicetree.cb "A device needs to be listed in the mainboard devicetree.cb if it requires more setup than standard PCI initialization (resource allocation) \ A device needs to be listed in the mainboard devicetree.cb if it requires more setup than standard PCI initialization (resource allocation). \ Typically, that includes the CPU, northbridge, southbridge, and Super I/O. \ These devices are usually required for system specific configuration as well as indicate the system bus structure (pci_domain)". As I understood during the coreboot PCI scan process some function (what is it name?) traverses this device tree and calls customized initialization via the device_operations and the chip_operations structures. So the question is... Can I don't specify some PCI devices on the mainboard in the device tree if they don't need additional initialization except to the allocation of resources? And why do I need to specify the device tree structure. Is there a function that traverses it and finds some device (without numeration) to initialize it? In this search that function needs the tree. Is the device tree passed then to the kernel of the operating system (modified)? As I can see the i2c is listed in the tree also (I am using the asus f2a85-m mainboard as an example). Does the searching of the SPD data is produced during the traversal of this tree? This question refers the other initialization (except PCI). Thank you very much for your advice. If you have any documentation or records on this matter - please share them. Sorry for any stupid questions until I can understand it. I am the beginner to this. Regards Maxim

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coreboot February 2017