coreboot November 2017

coreboot@coreboot.org

61 participants
110 discussions

Re: [coreboot] What’s the release plan for coreboot 4.7?
by Youness Alaoui 20 Nov '17

20 Nov '17

Hi, What happened with the plan for the 4.7 release? I thought it was supposed to be out at the end of October, now we're approaching the end of November. Was it forgotten, delayed or cancelled ? If delayed, what's the blocking issue ? Thanks, Youness. On Wed, Oct 4, 2017 at 11:24 AM, Martin Roth <gaumless(a)gmail.com> wrote: > The release will happen towards the end of the month. Generally I > try to have the release scheduled a bit before the month ends so > there's a little room to slip. I'll sit down this weekend and start > sorting out where we are and send out another email with release > plans. > > If there are any bugs in the bug tracker that people would > specifically like help with getting fixed before the next release, > please reply here. > > If developers could take a look at coverity and see if there are any > issues there that they can fix, that would be great. > > Please start testing any boards that you have and uploading the > results to the board-status repo so we know what's working. If you > have boards that don't boot, please reply here, and try to bisect the > issue to find where it stopped working. > > Martin > > > > On Tue, Oct 3, 2017 at 9:33 AM, Paul Menzel > <paulepanter(a)users.sourceforge.net> wrote: >> Dear coreboot folks, >> >> >> It’s October and coreboot 4.7 is supposed to be tagged in this month. >> >> Are there more specific plans already, when the release will happen? >> >> >> Thanks, >> >> Paul >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] how to Compile apollolake soc
by Zoran Stojsavljevic 20 Nov '17

20 Nov '17

First email thread to read ([coreboot] Intel Leaf Hill Coreboot Trouble): https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html Second community thread to read (to get the idea about APL-I IFWI): https://embedded.communities.intel.com/thread/13129 Please, let us know if these threads are helpful! Zoran On Mon, Nov 20, 2017 at 1:58 PM, chinmoy ghosh <chinmoyghosh2001(a)gmail.com> wrote: > It is a appoloke soc . > I am able to do make but it is only compiling ramstage/* . > I want to compile ./src/soc/intel/common/block/i2c/lpss_i2c.c and which > is linked from Appololake SOC. In menuconfig , i can't select the > Appololake SOC . > Any help . > > Regards > Chinmoy > > On Mon, Nov 20, 2017 at 6:04 PM, Naresh G. Solanki < > naresh.solanki.2011(a)gmail.com> wrote: > >> Hi Chinmoy, >> >> Which main board are you trying to build? >> >> Did you had chance to go through the core boot wiki: >> https://www.coreboot.org/Developer_Manual >> >> Regards, >> Naresh >> >> On Nov 20, 2017 4:14 PM, "chinmoy ghosh" <chinmoyghosh2001(a)gmail.com> >> wrote: >> >> Hi , >> I need to compile intel /apollolake SOC but in menuconfig i am not able >> to see. How to compile that ? >> Thanks in Advance >> Chinmoy >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> >> >> > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] how to Compile apollolake soc
by chinmoy ghosh 20 Nov '17

20 Nov '17

It is a appoloke soc . I am able to do make but it is only compiling ramstage/* . I want to compile ./src/soc/intel/common/block/i2c/lpss_i2c.c and which is linked from Appololake SOC. In menuconfig , i can't select the Appololake SOC . Any help . Regards Chinmoy On Mon, Nov 20, 2017 at 6:04 PM, Naresh G. Solanki < naresh.solanki.2011(a)gmail.com> wrote: > Hi Chinmoy, > > Which main board are you trying to build? > > Did you had chance to go through the core boot wiki: https://www.coreboot. > org/Developer_Manual > > Regards, > Naresh > > On Nov 20, 2017 4:14 PM, "chinmoy ghosh" <chinmoyghosh2001(a)gmail.com> > wrote: > > Hi , > I need to compile intel /apollolake SOC but in menuconfig i am not able to > see. How to compile that ? > Thanks in Advance > Chinmoy > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] how to Compile apollolake soc
by Naresh G. Solanki 20 Nov '17

20 Nov '17

Hi Chinmoy, Which main board are you trying to build? Did you had chance to go through the core boot wiki: https://www.coreboot.org/Developer_Manual Regards, Naresh On Nov 20, 2017 4:14 PM, "chinmoy ghosh" <chinmoyghosh2001(a)gmail.com> wrote: Hi , I need to compile intel /apollolake SOC but in menuconfig i am not able to see. How to compile that ? Thanks in Advance Chinmoy -- coreboot mailing list: coreboot(a)coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

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how to Compile apollolake soc
by chinmoy ghosh 20 Nov '17

20 Nov '17

Hi , I need to compile intel /apollolake SOC but in menuconfig i am not able to see. How to compile that ? Thanks in Advance Chinmoy

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Re: [coreboot] ASUS P2-99 with P2B config
by Keith Hui 20 Nov '17

20 Nov '17

Hi Branden, On Sun, Nov 19, 2017 at 7:43 PM, Branden Waldner <scruffy99(a)gmail.com> wrote: > Keith, I've attached the dmesg from running a build with the acpi > patch you had me listed as a reviewer on - > https://review.coreboot.org/#/c/22473/ > Also, I wouldn't really consider myself as qualified for reviewing > code, but I'll gladly test it. Thanks for your report. I used the "reviewer" mechanism as a way to let you know I have a patch up you'll want to test. > I guess that's it, I think I mentioned everything I was planning to. > I've got several things to look into and try to figure out. I also > have several other boards that have supported chipsets that might be > interesting to work on as well, but I should probably stick with this > one, for now, to try to get it sorted out better and to learn more > about about working with coreboot. BX is a good one to learn coreboot on, because it well predates ME or any of that crap. :) > It's still throwing acpi errors. Is having color codes in the log > okay? I can avoid them in the future if it's a bother. Your dmesg indicates the external ACPI nodes that this patch is supposed to remove remained in your copy. First try "make clean" and build again to make sure all the code that are to be patched are actually patched. Second, 22473 depends on 21671 which introduces the reworked PIIX4E ASL with the offending bits omitted, so make sure you have it applied to your build. 22473 itself then pulls ASL in 21671 and not the original, facilitating its removal. > > As for getting flashrom working, I didn't get anywhere. I tried > writing eash of the piix gpos high and low and that didn't help, > though I did end up killing the fan by setting gpo0 low. > > I actually flashed the asus p2b bios to it and the board booted and > ran fine. Flashrom still didn't work, but aflash still did. It doesn't > make sense, flashrom is supposed to work on the p2b and if there was > something needed for board enable on the p2-99 (and not p2b), then > aflash shouldn't work while running p2b bios. The boards look the same > though, the only differences I can find are the 440ZX northbridge, the > unpopulated third ram slot, and the lack of the hardware monitor chip > (fan and voltage). You have "-p internal" on the command line? > I'd like to try putting together a dual flash, but the wiki seems a > bit lacking in details. It sounds like the idea is to connect vcc to > the chip enable pin with a switch and pull up resister, but doesn't > actually specify much. Is leaving the chip enable on the other other > flash chip floating okay or should it really be connected to ground? > (With another resister?) Is there a simple and cheap hardware setup to > switch this electronically for automated testing /.recovery? I > shouldn't have a problem with the soldering, I'd just like to know a > bit more about it before trying it. I'd prefer not killing the board > by screwing it up ( or messing up a hot swap). Even without flashrom > support, this would allow me to keep the asus bios on one chip and > coreboot on the other and just having the asus bios on one chip for > booting just to switch back and flash the other chip. I've been hotswapping chips on my p2b-ls. I only lightly press my chip into the socket, just tight enough it won't pop out on its own, but loose enough I can lift it off by finger. > > Anyway, back to the actual system. There's is a couple of quirks / > issues I need to look into yet. > > When booting with only one ram stick, the keyboard doesn't work with > seabios and loading grub 2 from disk. This has happened otherwise > (with two ram sticks), but rarely. Even with the seabios keyboard > delay set really high (5000 milli seconds), it still doesn't work. > Linux has no problem once it's booted though. > > Now for the really stange part, that got me to try removing a ram > stick in the first place. When rebooting from a uclibc hardened gentoo > (kernel 4.12) system and running memtest86+, it throws errors in > test(s) 3/4. This only happens after rebooting from that setup - not > debian stretch with linux 4.9 or 4.12bpo - and not after another > reboot. This happens with the debian, gentoo uclibc hardened, or > coreboot versions of memtest86+. This doesn't happen with the factory > bios. I tested this numerous times to verify what was happening - > marking down each test I ran.. > > Coreboot seems to setup the ram differently then the factory bios. > Memtest86+ lists the ram speed as 217MB/s (coreboot) vs 258MB/s > (bios), but with much better sysbench memory results with coreboot - > with the gentoo uclibc hardened setup with a 10 second test it got > double the bios did and with debian and sysbench memory set to 1600MB > (what the coreboot / gentoo uclibc hardened setup got in 10 seconds) > the debian it performed around four times better with coreboot vs > bios. And this is with passing eight couninous passes of memtest86+ > when not running into the issue above. Is coreboot just using more > aggressive settings then the factory bios uses? I'm fine with coreboot > resulting in better performence then the factory bios! When you build again, enable: - Debugging/Verbose RAM init debug messages - Console/Send console output to a CBMEM buffer Then get us the console log via # cbmem -c You'll also need to do some BX configuration dumps with OEM and coreboot, so I can compare where the differences are. If possible I'd like to catch a dump with all memory combinations - 1, 2, 1+2. One set with coreboot and one set with OEM. The command to do this dump is: # lspci -s 0:0:0 -xxx I can disassemble my copy of P2B bios and see what it does. But do know that when I did the 440BX ram init code in 2010, I only did for boards with 4 slots, 3-slot boards were never really done because I don't have such a board. Plus, the logic is modeled after the ram init code in the oem boot block, with just enough init to get ram going for later stages and made no attempts to optimize for latency or speed. There probably is room for improvement. > Another note, several of the P2* board wiki pages list the L2 cache as > not working with coreboot. I ran into the L2 cache not working when I > originally tested this board with coreboot while running a pentium 2 > at 400MHz. It seems that this was an issue with pentium 2 L2 cache > enablement, should the wiki document this as an issue with pentium 2 > processsors? (specific versions?) The jumpers on the board were > actually set to 5.5 multiplier @ 100 MHz (like the current pentium iii > setup) and it didn't seem to have any affect - coreboot or bios. I > didn't do any benchmark tests though. I ported the Pentium II/III L2 cache init from coreboot v1 also around 2010 and L2 should work now. Wiki likely hasn't been updated in forever... If in doubt, the console output should tell if L2 cache works. The CPU of this era just don't look at the multiplier setting at all. To overclock we have to crank up the bus frequency. > I also ended up testing the system with a pair of floppy drives, since > it's marked as untested on the p2b wiki page. Both worked fine with > the bios, but they didn't show up with seabios or after booting linux. > I don't particularly care about floppy support though, unless I wanted > to run it diskless and didn't have enough room on the flash for a > proper ipxe setup. PS/2 mouse works fine though - it is also marked > untested. > Thanks for these reports. Double check the devicetree.cb. Does it have pnp device 3f0.0 "on"? This is the floppy.

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Re: [coreboot] ASUS P2-99 with P2B config
by Branden Waldner 20 Nov '17

20 Nov '17

Keith, I've attached the dmesg from running a build with the acpi patch you had me listed as a reviewer on - https://review.coreboot.org/#/c/22473/ It's still throwing acpi errors. Is having color codes in the log okay? I can avoid them in the future if it's a bother. Also, I wouldn't really consider myself as qualified for reviewing code, but I'll gladly test it. As for getting flashrom working, I didn't get anywhere. I tried writing eash of the piix gpos high and low and that didn't help, though I did end up killing the fan by setting gpo0 low. I actually flashed the asus p2b bios to it and the board booted and ran fine. Flashrom still didn't work, but aflash still did. It doesn't make sense, flashrom is supposed to work on the p2b and if there was something needed for board enable on the p2-99 (and not p2b), then aflash shouldn't work while running p2b bios. The boards look the same though, the only differences I can find are the 440ZX northbridge, the unpopulated third ram slot, and the lack of the hardware monitor chip (fan and voltage). I'd like to try putting together a dual flash, but the wiki seems a bit lacking in details. It sounds like the idea is to connect vcc to the chip enable pin with a switch and pull up resister, but doesn't actually specify much. Is leaving the chip enable on the other other flash chip floating okay or should it really be connected to ground? (With another resister?) Is there a simple and cheap hardware setup to switch this electronically for automated testing /.recovery? I shouldn't have a problem with the soldering, I'd just like to know a bit more about it before trying it. I'd prefer not killing the board by screwing it up ( or messing up a hot swap). Even without flashrom support, this would allow me to keep the asus bios on one chip and coreboot on the other and just having the asus bios on one chip for booting just to switch back and flash the other chip. Anyway, back to the actual system. There's is a couple of quirks / issues I need to look into yet. When booting with only one ram stick, the keyboard doesn't work with seabios and loading grub 2 from disk. This has happened otherwise (with two ram sticks), but rarely. Even with the seabios keyboard delay set really high (5000 milli seconds), it still doesn't work. Linux has no problem once it's booted though. Now for the really stange part, that got me to try removing a ram stick in the first place. When rebooting from a uclibc hardened gentoo (kernel 4.12) system and running memtest86+, it throws errors in test(s) 3/4. This only happens after rebooting from that setup - not debian stretch with linux 4.9 or 4.12bpo - and not after another reboot. This happens with the debian, gentoo uclibc hardened, or coreboot versions of memtest86+. This doesn't happen with the factory bios. I tested this numerous times to verify what was happening - marking down each test I ran.. Coreboot seems to setup the ram differently then the factory bios. Memtest86+ lists the ram speed as 217MB/s (coreboot) vs 258MB/s (bios), but with much better sysbench memory results with coreboot - with the gentoo uclibc hardened setup with a 10 second test it got double the bios did and with debian and sysbench memory set to 1600MB (what the coreboot / gentoo uclibc hardened setup got in 10 seconds) the debian it performed around four times better with coreboot vs bios. And this is with passing eight couninous passes of memtest86+ when not running into the issue above. Is coreboot just using more aggressive settings then the factory bios uses? I'm fine with coreboot resulting in better performence then the factory bios! Another note, several of the P2* board wiki pages list the L2 cache as not working with coreboot. I ran into the L2 cache not working when I originally tested this board with coreboot while running a pentium 2 at 400MHz. It seems that this was an issue with pentium 2 L2 cache enablement, should the wiki document this as an issue with pentium 2 processsors? (specific versions?) The jumpers on the board were actually set to 5.5 multiplier @ 100 MHz (like the current pentium iii setup) and it didn't seem to have any affect - coreboot or bios. I didn't do any benchmark tests though. I also ended up testing the system with a pair of floppy drives, since it's marked as untested on the p2b wiki page. Both worked fine with the bios, but they didn't show up with seabios or after booting linux. I don't particularly care about floppy support though, unless I wanted to run it diskless and didn't have enough room on the flash for a proper ipxe setup. PS/2 mouse works fine though - it is also marked untested. I guess that's it, I think I mentioned everything I was planning to. I've got several things to look into and try to figure out. I also have several other boards that have supported chipsets that might be interesting to work on as well, but I should probably stick with this one, for now, to try to get it sorted out better and to learn more about about working with coreboot.

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Re: [coreboot] Not able to compile drivers
by chinmoy ghosh 17 Nov '17

17 Nov '17

I am not sure my last email approach may be not good. but one thing : how to compile : ./src/soc/intel/common/block/i2c/lpss_i2c.c . In my project i am compiling only libpayload. and need to to compile this i2c project too, Regards Chiinmoy On Fri, Nov 17, 2017 at 4:05 PM, chinmoy ghosh <chinmoyghosh2001(a)gmail.com> wrote: > Thanks for reply. > > Requirement : > I am working for Intel Apollo Lake SOC. > I need to enable a power chip which sits on I2c bus and reset the chip > via gpio pin .So i need to write a slave driver to access the chip. > > Static Analysis by me : > Before that , i2c master should be there . I feel lpss_i2c.c can help the > same. > I called the lpss_i2c_init function from external/coreboot/payloads/libpayload/arch/x86/main.c > and compiling with libpayload.a . > let me know if i am right upto this ?. if it is then following questions > are : > 1) how to access GPIO register to ser one or zero > 2) how to do i2c slave write for that chip ? any api for that ? > > > Regards > Chinmoy > > > On Fri, Nov 17, 2017 at 2:04 PM, Paul Menzel <paulepanter@users. > sourceforge.net> wrote: > >> Dear Chinmoy, >> >> >> Am Donnerstag, den 16.11.2017, 17:48 +0530 schrieb chinmoy ghosh: >> > I am new to coreboot. >> >> Welcome! >> >> > I am able to clone the coreboot and able to compile for x86 arch. >> > I am not able to select any drivers in the menuconfig. I want compile >> some >> > coreboot/src/drivers/i2c drivers. >> >> I assume these are dependent on the board. Please elaborate on your >> goal, that means what I2C driver do you need, and what board do you >> work on, and give all the necessary details, like what commit hash you >> use. >> >> >> Thanks, >> >> Paul >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] Not able to compile drivers
by Paul Menzel 17 Nov '17

17 Nov '17

Dear Chinmoy, Am Donnerstag, den 16.11.2017, 17:48 +0530 schrieb chinmoy ghosh: > I am new to coreboot. Welcome! > I am able to clone the coreboot and able to compile for x86 arch. > I am not able to select any drivers in the menuconfig. I want compile some > coreboot/src/drivers/i2c drivers. I assume these are dependent on the board. Please elaborate on your goal, that means what I2C driver do you need, and what board do you work on, and give all the necessary details, like what commit hash you use. Thanks, Paul

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Not able to compile drivers
by chinmoy ghosh 16 Nov '17

16 Nov '17

Hi , I am new to coreboot .I am able to clone the coreboot and able to compile for x86 arch . I am not able to select any drivers in the menuconfig . I want compile some coreboot/src/drivers/i2c drivers. Waiting for your help . Regards Chinmoy

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coreboot November 2017