coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

Re: [coreboot] coreboot on KGPE-D16 "boot-loops"
by Pi Van Den Cirkel 09 Jan '17

09 Jan '17

When I use different RAM modules, the process does not "boot-loop" (reset) but blocks at: ```ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned``` RAM Module: Nanya 4GB 2Rx8 PC3-10600E-9-10-E0 1333 ECC (NT4GC72B8PG0NF-CG) CB LOG: https://paste.debian.net/hidden/d38ffc04/ On Sun, Jan 8, 2017 at 5:46 AM, Pi Van Den Cirkel <opdecirkel(a)gmail.com> wrote: > Hi, > > I need help with issue i have with coreboot on KGPE-D16 where it > "boot-loops" (resets) indefinitely during RAM init (see the log below > which repeats). The board works with the stock BIOS. > > Board version: 1.03G > CPUs: 2x AMD Opteron 6274 > RAM: HMT42GR7CMR4C-G7 D8 AC - two modules, one module in slot A2 > (CPU1) and another in E2 (CPU2), for total of 32Gb > > git commit id: f3e26796 (latest master) > > Coreboot log: https://paste.debian.net/hidden/83d4816c/ > Coreboot config: https://paste.debian.net/907604/ > > Thanks

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Re: [coreboot] coreboot on KGPE-D16 "boot-loops"
by David 09 Jan '17

09 Jan '17

Hello, I had the same issue a couple of months ago. Could you try to disable serial and see if it helps ? Generic Drivers -> Serial Port on SuperIO (untick) Cheers

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Re: [coreboot] F2A-85M: Different VGA BIOS needed after CPU Upgrade?
by Daniel Kulesz 09 Jan '17

09 Jan '17

Hi John, > It sounds to me as though the PCI id's of the graphics card for the > upgraded CPU may be different (I could be totally wrong about that, so I > defer to others on the list if I'm barking up the wrong tree) and your > coreboot image may need to be updated accordingly. Of course, it could > also be the video BIOS that's the problem as you've suggested. Thank you for the hint. I inspected that, but the PCI-IDs actually look the same: 00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Trinity [Radeon HD 7480D] [1002:9993] (A4-5300) and 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Richland [Radeon HD 8670D] (prog-if 00 [VGA controller]) (A10-6700) Looks like the VGA BIOS is really different: # diff vgabios_a4-5300.bin vgabios_a10_6700.bin Binary files vgabios_a4-5300.bin and vgabios_a10_6700.bin differ Guess I will have to to "update" the VGA BIOS then. Cheers, Daniel > > Hi Daniel, > > > Kind Regards, > > John. > > > On 28/06/16 09:24, Daniel Kulesz via coreboot wrote: > > Hi folks, > > > > I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works. > > > > Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even when using the extractor tool). > > > > Cheers, Daniel > >

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Speaker for Mix-IT wanted (Lyon, April 20th/21st, 2017)
by Paul Menzel 08 Jan '17

08 Jan '17

Dear coreboot folks, At the last community meeting Philipp reported, that we were asked to present coreboot at Mix-IT [1]. Is there somebody with time, who would be willing to present the coreboot project there? That’d be awesome. Thanks, Paul [1] https://www.mix-it.fr/

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coreboot on KGPE-D16 "boot-loops"
by Pi Van Den Cirkel 08 Jan '17

08 Jan '17

Hi, I need help with issue i have with coreboot on KGPE-D16 where it "boot-loops" (resets) indefinitely during RAM init (see the log below which repeats). The board works with the stock BIOS. Board version: 1.03G CPUs: 2x AMD Opteron 6274 RAM: HMT42GR7CMR4C-G7 D8 AC - two modules, one module in slot A2 (CPU1) and another in E2 (CPU2), for total of 32Gb git commit id: f3e26796 (latest master) Coreboot log: https://paste.debian.net/hidden/83d4816c/ Coreboot config: https://paste.debian.net/907604/ Thanks

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Re: [coreboot] "FCH SPI: Too much to write" on KGPE-D16
by Timothy Pearson 06 Jan '17

06 Jan '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/05/2017 04:33 AM, Iru Cai wrote: > Hello, > > I've set up a computer with Asus KGPE-D16 recently. I use an Winbond > W25Q64.V 8M flash chip and tested with this config with only ROM size > changed: > > https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16… > > And it can boot to my OS on disk. However, after I enabled the serial > console, I can only see: > "FCH SPI: Too much to write. Does your SPI chip driver use > spi_crop_chunk()?" Do you see any other messages at all from a cold start (i.e. AC power removed from the system, then reapplied after 15 seconds while the serial console is being logged)? I have not personally tested the 8M chips; it could be that there is an issue with coreboot's generic driver for those devices. I know it's not a general issue with large Flash chips since the 16M chips work fine. Thanks! - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYbn7XAAoJEK+E3vEXDOFbIasIAIb1myve1e7FuuGcsOsPztM7 OUiIl2ru/jcowbIpAjpTmvWeuGg+FMyf/qmVAZC0dDDoj0prGxmax/SeiLp3N2E7 m/Dms9MKa6p90XuZe+KBATwQi7uBoMrrYQzJ5ZDPlaPsaiPsD7jPQA7sl+522b+m Y58pD1b4ZjLFydjHp2VPBqpcrLaVzv8Trubka2jqfDFsYmrwQeWswFG+LS4BdwgM dcop2VpHybY6tX/PEoGyOYYprOiNbmH4kY//HSWfK7aRLUazShW0+svFHGYjzcuK MdfBIJoAnuNc9Dk4uauJC2uFVHzYkXWeG23YyjZg2guGrhTmOLwEDetXeV1V3yg= =rd9i -----END PGP SIGNATURE-----

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 06 Jan '17

06 Jan '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 43 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1368307: Integer handling issues (DIVIDE_BY_ZERO) /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c: 1107 in procConfig() ________________________________________________________________________________________________________ *** CID 1368307: Integer handling issues (DIVIDE_BY_ZERO) /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c: 1107 in procConfig() 1101 Seed_Total = 0x15; 1102 } 1103 if (pDCTData->Status[DCT_STATUS_REGISTERED]) 1104 Seed_Total += ((AddrCmdPrelaunch)?0x10:0x0); 1105 1106 /* Adjust seed for the minimum platform supported frequency */ >>> CID 1368307: Integer handling issues (DIVIDE_BY_ZERO) >>> In expression "(int64_t)Seed_Total * fam15h_freq_tab[MemClkFreq] * 100LL / (mctGet_NVbits(4) * 100)", division by expression "mctGet_NVbits(4) * 100" which may be zero has undefined behavior. 1107 Seed_Total = (int32_t) (((((int64_t) Seed_Total) * 1108 fam15h_freq_tab[MemClkFreq] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); 1109 1110 Seed_Gross = (Seed_Total >> 5) & 0x1f; 1111 Seed_Fine = Seed_Total & 0x1f; 1112 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Building 4.5 from release sources
by Trammell Hudson 06 Jan '17

06 Jan '17

When I build coreboot 4.5 from the release sources it is necessary to download the coreboot-blobs-4.5.tar.xz file and it looks like there might be a dependency now on the 3rdparty/vboot tree as well since cbfs.h includes vb2_api.h: https://github.com/coreboot/coreboot/blob/master/src/commonlib/include/comm… When building from git it checks out the correct submodule, so this is only a problem for me with releases. Is there an official release tar for vboot sources? I don't see one in https://www.coreboot.org/releases/. -- Trammel

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Re: [coreboot] Building 4.5 from release sources
by Peter Stuge 05 Jan '17

05 Jan '17

Aaron Durbin via coreboot wrote: > This was discussed around a month ago on #coreboot, iirc. That's not really good enough, IMHO. So far, coreboot was always self-contained. It even goes so far as to build its own toolchain. Creating mandatory dependencies which may actually not always be neccessary is simply poor software engineering, and not something I think that we should be doing. Let's try to fix it! Is there any technical reason *not* to decouple coreboot source from vboot source completely? //Peter

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"FCH SPI: Too much to write" on KGPE-D16
by Iru Cai 05 Jan '17

05 Jan '17

Hello, I've set up a computer with Asus KGPE-D16 recently. I use an Winbond W25Q64.V 8M flash chip and tested with this config with only ROM size changed: https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16… And it can boot to my OS on disk. However, after I enabled the serial console, I can only see: "FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()?" And the machine cannot boot. Has anyone seen this issue before? Thanks, Iru -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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coreboot January 2017