coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

chat.coreboot.org is on
by Patrick Georgi 13 Jan '17

13 Jan '17

Hi all, we've set up a mattermost instance on https://chat.coreboot.org/ in the hope to lower the barriers to entry into our community. It comes with a bridge to IRC, history (but not web-indexable, which was a major concern with IRC logs so far) and the ability to start topic channels that are discoverable yet separate from the main discussion. See you there, Patrick

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New toolchain coming - Please test your boards with it
by Martin Roth 12 Jan '17

12 Jan '17

coreboot intends to update our toolchain soon, and we'd like to get it thoroughly tested before we do, so we need everyone's help. Please download the toolchain patch, build the new toolchain, then build and test any boards you're working on with it. You can either reply to this thread with your results, or email me directly. https://review.coreboot.org/#/c/17189/ Another option for testing the new toolchain is to use the docker coreboot-sdk image if you have a decent internet connection. This downloads about 1GB of docker containers which decompresses to about 3GB. From the coreboot directory, after setting up your config file, run: % docker run -u root -it -v $PWD:/home/coreboot/coreboot --rm coreboot/coreboot-sdk:test /bin/bash -c "cd /home/coreboot/coreboot && make clean && make" This leaves build files owned by root, so you'll need to chown them back: % sudo chown -R $(whoami):$(id -gn $(whoami)) . Thanks for your help. Martin

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Re: [coreboot] Question about PCIe separate reference clock
by Zoran Stojsavljevic 12 Jan '17

12 Jan '17

> Zheng: We do NOT sync these two. You must, as my best understanding is. > Zheng: yes. Asynchronous. They should (be forced to) be made synchronous (on the extension card). > The VPX connector does not have a PCIe ref clock signal, so we can not send > CPU PCIe ref clock to device. The PCIe spec says if the separate refclk on devices > should be 100MHz ± 300PPM, with SSC off. I doubt. There is no way that two asynchronized clocks, however they are locally stabilized, be synchronized. After some (?) time they'll drift beyond 50% of the base cycle. Whatever this some (?) time will be. This is why when you (by)pass by wire local reference clock from CPU to extension card, data transfer seamlessly (synchronously) works. I need to see VPX connector pin layout. It must be somewhere some info passed/encoded to PCIe card via VPX connector with info about the clock (some diff signal passed, or some encoded sync), or integrated in some other signal (which must be extracted after passing the connector to the extension card). Do you have some reference design you can compare your proprietary design with? Predrag can also (he is HW person domain) put/comment some of his thoughts on this thread (if Predrag wants). As well as some other people (from Coreboot list). Zoran _______ On 1/12/17, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Q: do you use local xtal attached to Si52111-B5 to generate local PCIe > 25MHz clock? > > Zheng: yes > > > Q: If you dothis, my next question is how you synchronize these two clocks: > Local > PCIe 25 MHz and common reference clock from CPU? > > Zheng: We do NOT sync these two. > > Q: Since these two clocks, as I understand above scenario, are > asynchronous to each other?! > > Zheng: yes. Asynchronous. > > > The VPX connector does not have a PCIe ref clock signal, so we can not send > CPU PCIe ref clock to > > device. The PCIe spec says if the separate refclk on devices should be > 100MHz ± 300PPM, with SSC > > off. We believe our board meet this requirement. So we doubt the problem > lies in PCI configration space. > > > Zheng > > > ________________________________ > From: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> > Sent: Thursday, January 12, 2017 9:22 AM > To: Zheng Bao; Predrag Vidic > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] Question about PCIe separate reference clock > > Hello Zheng, > > For decades, I've been FW/SW engineer, but I do understand a little > bit of a HW. I have looked into the Si52111-B5 data sheet for > clarification. > > My problem here is to understand, your use case: do you use local xtal > attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do > this, my next question is how you synchronize these two clocks: Local > PCIe 25 MHz and common reference clock from CPU? > > Since these two clocks, as I understand above scenario, are > asynchronous to each other?! > > Please, clarify for us your use case. > > Thank you, > Zoran > _______ > > On 1/12/17, Zheng Bao <fishbaoz(a)hotmail.com> wrote: >> Our VPX design uses separate reference clock source, which is Si52111-B5 >> (No >> spread), instead of common ref clock from CPU. >> Now The system is unstable. Reading PCIE configuration space is unstable >> too. (If we add some fly wire to make it work with common ref clock, the >> system becomes stable.) >> >> (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit >> indicates >> that the >> component uses the same physical reference clock that the >> platform provides on the connector. If the device uses an >> independent clock irrespective of the presence of a reference >> clock on the connector, this bit must be clear. >> For a multi-Function device, each Function must report the >> same value for this bit.) >> >> Based on my understanding, the BIOS need to read bit "Slot Clock >> Configurationclear" to see if >> separate ref clock is used. BIOS then write bit "Common Clock >> Configuration". >> >> On our board, the bit "Slot Clock Configuration" is always 1, which I >> assume >> should be 0. >> >> My question is, how the hardware affect the bit "Slot Clock >> Configuration"? >> How do we need to design our board to make the bit "Slot Clock >> Configuration" be 0? >> >> Thanks. >> >> Zheng >> >> >

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Re: [coreboot] Question about PCIe separate reference clock
by Predrag Vidic 12 Jan '17

12 Jan '17

Hi Zheng, Without knowing the particular solution for the PCIe transmitter you have on your board, I'd check refclk pins on your design for the proper termination. The problem can be in irregular readings from the pins. Reragds, Predrag On Thu, Jan 12, 2017 at 3:26 PM, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Q: do you use local xtal attached to Si52111-B5 to generate local PCIe > 25MHz clock? > > Zheng: yes > > > Q: If you dothis, my next question is how you synchronize these two > clocks: Local > PCIe 25 MHz and common reference clock from CPU? > > Zheng: We do NOT sync these two. > > > Q: Since these two clocks, as I understand above scenario, are > asynchronous to each other?! > > Zheng: yes. Asynchronous. > > > The VPX connector does not have a PCIe ref clock signal, so we can not > send CPU PCIe ref clock to > > device. The PCIe spec says if the separate refclk on devices should be > 100MHz ± 300PPM, with SSC > > off. We believe our board meet this requirement. So we doubt the problem > lies in PCI configration space. > > > Zheng > > > > ------------------------------ > *From:* Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> > *Sent:* Thursday, January 12, 2017 9:22 AM > *To:* Zheng Bao; Predrag Vidic > *Cc:* coreboot(a)coreboot.org > *Subject:* Re: [coreboot] Question about PCIe separate reference clock > > Hello Zheng, > > For decades, I've been FW/SW engineer, but I do understand a little > bit of a HW. I have looked into the Si52111-B5 data sheet for > clarification. > > My problem here is to understand, your use case: do you use local xtal > attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do > this, my next question is how you synchronize these two clocks: Local > PCIe 25 MHz and common reference clock from CPU? > > Since these two clocks, as I understand above scenario, are > asynchronous to each other?! > > Please, clarify for us your use case. > > Thank you, > Zoran > _______ > > On 1/12/17, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > > Our VPX design uses separate reference clock source, which is Si52111-B5 > (No > > spread), instead of common ref clock from CPU. > > Now The system is unstable. Reading PCIE configuration space is unstable > > too. (If we add some fly wire to make it work with common ref clock, the > > system becomes stable.) > > > > (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit > indicates > > that the > > component uses the same physical reference clock that the > > platform provides on the connector. If the device uses an > > independent clock irrespective of the presence of a reference > > clock on the connector, this bit must be clear. > > For a multi-Function device, each Function must report the > > same value for this bit.) > > > > Based on my understanding, the BIOS need to read bit "Slot Clock > > Configurationclear" to see if > > separate ref clock is used. BIOS then write bit "Common Clock > > Configuration". > > > > On our board, the bit "Slot Clock Configuration" is always 1, which I > assume > > should be 0. > > > > My question is, how the hardware affect the bit "Slot Clock > Configuration"? > > How do we need to design our board to make the bit "Slot Clock > > Configuration" be 0? > > > > Thanks. > > > > Zheng > > > > >

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Re: [coreboot] Question about PCIe separate reference clock
by Kyösti Mälkki 12 Jan '17

12 Jan '17

On Thu, Jan 12, 2017 at 9:15 AM, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Our VPX design uses separate reference clock source, which is Si52111-B5 > (No spread), instead of common ref clock from CPU. > > Now The system is unstable. Reading PCIE configuration space is unstable > too. (If we add some fly wire to make it work with common ref clock, the > system becomes stable.) > > Can you send lspci -xxxx output from this stable common-ref-clock config? > > (abstracted from PCIe spec: 12 Slot Clock Configuration – This bit > indicates that the > component uses the same physical reference clock that the > platform provides on the connector. If the device uses an > independent clock irrespective of the presence of a reference > clock on the connector, this bit must be clear. > For a multi-Function device, each Function must report the > same value for this bit.) > > Based on my understanding, the BIOS need to read bit "Slot Clock > Configurationclear" to see if > > separate ref clock is used. BIOS then write bit "Common Clock > Configuration". > > > > On our board, the bit "Slot Clock Configuration" is always 1, which I > assume should be 0. > > > > My question is, how the hardware affect the bit "Slot Clock > Configuration"? How do we need to design our board to make the bit "Slot > Clock Configuration" be 0? > Speculating below that some AMD SoC is involved in your design. Making that bit appear as 0 is silicon specific, for You it should be possible to ask other AMD engineers directly the conditions when PCIe root ports will have this bit set as 0. NDA'd docs from AMD that are within my reach do not have clear specs on PCIe refclock AC characteristics when running in internal clocking mode. Since PCIe separate refclock architecture has more strict requirements for clock jitter, AMD SoC's might fail there unless you are bootstrapping them to external reference clock mode. Regards, Kyösti Mälkki

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Re: [coreboot] Question about PCIe separate reference clock
by Zheng Bao 12 Jan '17

12 Jan '17

Q: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock? Zheng: yes Q: If you dothis, my next question is how you synchronize these two clocks: Local PCIe 25 MHz and common reference clock from CPU? Zheng: We do NOT sync these two. Q: Since these two clocks, as I understand above scenario, are asynchronous to each other?! Zheng: yes. Asynchronous. The VPX connector does not have a PCIe ref clock signal, so we can not send CPU PCIe ref clock to device. The PCIe spec says if the separate refclk on devices should be 100MHz ± 300PPM, with SSC off. We believe our board meet this requirement. So we doubt the problem lies in PCI configration space. Zheng ________________________________ From: Zoran Stojsavljevic <zoran.stojsavljevic(a)gmail.com> Sent: Thursday, January 12, 2017 9:22 AM To: Zheng Bao; Predrag Vidic Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Question about PCIe separate reference clock Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into the Si52111-B5 data sheet for clarification. My problem here is to understand, your use case: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do this, my next question is how you synchronize these two clocks: Local PCIe 25 MHz and common reference clock from CPU? Since these two clocks, as I understand above scenario, are asynchronous to each other?! Please, clarify for us your use case. Thank you, Zoran _______ On 1/12/17, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Our VPX design uses separate reference clock source, which is Si52111-B5 (No > spread), instead of common ref clock from CPU. > Now The system is unstable. Reading PCIE configuration space is unstable > too. (If we add some fly wire to make it work with common ref clock, the > system becomes stable.) > > (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates > that the > component uses the same physical reference clock that the > platform provides on the connector. If the device uses an > independent clock irrespective of the presence of a reference > clock on the connector, this bit must be clear. > For a multi-Function device, each Function must report the > same value for this bit.) > > Based on my understanding, the BIOS need to read bit "Slot Clock > Configurationclear" to see if > separate ref clock is used. BIOS then write bit "Common Clock > Configuration". > > On our board, the bit "Slot Clock Configuration" is always 1, which I assume > should be 0. > > My question is, how the hardware affect the bit "Slot Clock Configuration"? > How do we need to design our board to make the bit "Slot Clock > Configuration" be 0? > > Thanks. > > Zheng > >

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Re: [coreboot] Question about PCIe separate reference clock
by Zoran Stojsavljevic 12 Jan '17

12 Jan '17

Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into the Si52111-B5 data sheet for clarification. My problem here is to understand, your use case: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do this, my next question is how you synchronize these two clocks: Local PCIe 25 MHz and common reference clock from CPU? Since these two clocks, as I understand above scenario, are asynchronous to each other?! Please, clarify for us your use case. Thank you, Zoran _______ On 1/12/17, Zheng Bao <fishbaoz(a)hotmail.com> wrote: > Our VPX design uses separate reference clock source, which is Si52111-B5 (No > spread), instead of common ref clock from CPU. > Now The system is unstable. Reading PCIE configuration space is unstable > too. (If we add some fly wire to make it work with common ref clock, the > system becomes stable.) > > (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates > that the > component uses the same physical reference clock that the > platform provides on the connector. If the device uses an > independent clock irrespective of the presence of a reference > clock on the connector, this bit must be clear. > For a multi-Function device, each Function must report the > same value for this bit.) > > Based on my understanding, the BIOS need to read bit "Slot Clock > Configurationclear" to see if > separate ref clock is used. BIOS then write bit "Common Clock > Configuration". > > On our board, the bit "Slot Clock Configuration" is always 1, which I assume > should be 0. > > My question is, how the hardware affect the bit "Slot Clock Configuration"? > How do we need to design our board to make the bit "Slot Clock > Configuration" be 0? > > Thanks. > > Zheng > >

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Question about PCIe separate reference clock
by Zheng Bao 12 Jan '17

12 Jan '17

Our VPX design uses separate reference clock source, which is Si52111-B5 (No spread), instead of common ref clock from CPU. Now The system is unstable. Reading PCIE configuration space is unstable too. (If we add some fly wire to make it work with common ref clock, the system becomes stable.) (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear. For a multi-Function device, each Function must report the same value for this bit.) Based on my understanding, the BIOS need to read bit "Slot Clock Configurationclear" to see if separate ref clock is used. BIOS then write bit "Common Clock Configuration". On our board, the bit "Slot Clock Configuration" is always 1, which I assume should be 0. My question is, how the hardware affect the bit "Slot Clock Configuration"? How do we need to design our board to make the bit "Slot Clock Configuration" be 0? Thanks. Zheng

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Re: [coreboot] power controller/serial port mux
by Carl-Daniel Hailfinger 10 Jan '17

10 Jan '17

On 10.01.2017 22:56, ron minnich wrote: > I need an ethernet-attached device for controlling power to 4 to 8 systems With Schuko plug this ethernet controlled power strip is pretty nice (they also have a USB-controlled variant) http://energenie.com/item.aspx?id=7557&lang=en > and also a serial port mux which can allow multiple users to go to > different systems. > > If there is a box that does both that's a plus. I figure this group > knows more than anybody about a good choice. To be honest, if you want a cheap and scalable solution with good electrical isolation, the solution I've seen quite often is to buy wirelessly controllable power sockets (pack of 4 retails for ~15 EUR in Germany). Wire up the power socket remote control with a raspberry pi and you're done. For serial ports, I just hooked up a bunch of USB-serial adapters to a Raspberry Pi. Then again, this solution is probably unusable for multi-user environments. Regards, Carl-Daniel

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Re: [coreboot] power controller/serial port mux
by Matt DeVillier 10 Jan '17

10 Jan '17

Ron, I've used one of these on another project for remote power control: http://www.digital-loggers.com/lpc.html -- seems to work reliably, and can be controlled via simply http(s) commands -Matt On Tue, Jan 10, 2017 at 3:56 PM, ron minnich <rminnich(a)gmail.com> wrote: > I need an ethernet-attached device for controlling power to 4 to 8 > systems, and also a serial port mux which can allow multiple users to go to > different systems. > > If there is a box that does both that's a plus. I figure this group knows > more than anybody about a good choice. > > thanks > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot January 2017