coreboot January 2017

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Re: [coreboot] Fund a TALOS Secure Workstation as coreboot build system
by ron minnich 17 Jan '17

17 Jan '17

The Talos was a noble effort. One way or another, we're going to get where we need to go.

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Re: [coreboot] Fund a TALOS Secure Workstation as coreboot build system
by Martin Roth 17 Jan '17

17 Jan '17

Hi Everyone, I suspect that everyone has already heard that unfortunately, the funding for Raptor Engineering's Talos workstation project was not successful, so I wanted to make a final post to wrap this up. Between 12 people, we had raised enough to buy the full system and a processor, and I'd like to once again thank everyone who committed money to helping the project. If you haven't read Timothy's final post, I thought it was fairly relevant, although I suspect that many of the people in the coreboot community already know many of his points. https://www.crowdsupply.com/raptor-computing-systems/talos-secure-workstati… Also in the final update, Timothy mentions some of the future projects that Raptor is planning to work on, including developing an open BMC board for the Asus KGPE-D16 board. If anyone would like to help fund that, or transfer any of the money that they were going to use to support the Talos project, I'll match contributions with the money I was going to put towards Talos. He also mentions that he's going to keep working on open-power solutions, so I'm definitely looking forward to seeing what happens with that. Martin On Mon, Dec 5, 2016 at 10:48 AM, Martin Roth <gaumless(a)gmail.com> wrote: > Update: > I've added coreboot's commitment to purchase a board and a processor > to the crowdsupply site. > > Board: 3700 > Processor: 1240 > > We've got $6,200 committed from 11 contributors. If things work out, > the rest of the money will be used for the additional components > needed, and an upgraded processor. > > Thanks to everyone who committed to supporting the purchase. > > Martin > > > On Thu, Nov 10, 2016 at 10:36 AM, Martin Roth <gaumless(a)gmail.com> wrote: >> Update: >> We've got $4400 promised, with 7 contributors. >> >> On Mon, Nov 7, 2016 at 2:22 PM, Martin Roth <gaumless(a)gmail.com> wrote: >>> >>> Update: >>> After the weekend, we're up to $3700 with 5 contributors. >>> >>> Martin >>> >>> On Sun, Nov 6, 2016 at 1:01 PM, David Hendricks >>> <david.hendricks(a)gmail.com> wrote: >>>> >>>> >>>> >>>> On Fri, Nov 4, 2016 at 9:36 AM, Martin Roth <gaumless(a)gmail.com> wrote: >>>>> >>>>> Is getting a Talos workstation as a build server something that people >>>>> are interested in contributing money for? >>>> >>>> >>>> Yes, this needs to happen. >>>> >>>>> >>>>> So far, we've got $2500 pledged from two contributors out of the $7500 >>>>> needed to get a server. >>>> >>>> >>>> I'll match up to $2000 worth of small/moderate pledges ($250 or less). So >>>> if 10 people pledge $200 I'll chip in $2000 to bring us to $6500. >>> >>> >>

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 17 Jan '17

17 Jan '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 38 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1368527: (UNINIT) /src/arch/riscv/mcall.c: 81 in mcall_set_timer() /src/arch/riscv/mcall.c: 84 in mcall_set_timer() ________________________________________________________________________________________________________ *** CID 1368527: (UNINIT) /src/arch/riscv/mcall.c: 81 in mcall_set_timer() 75 die("mcall_shutdown is currently not implemented"); 76 return 0; 77 } 78 79 uintptr_t mcall_set_timer(uint64_t when) 80 { >>> CID 1368527: (UNINIT) >>> Using uninitialized value "sp". 81 uint64_t *timecmp = HLS()->timecmp; 82 83 if (mcalldebug) 84 printk(BIOS_SPEW, 85 "hart %d: HLS %p: mcall timecmp@%p to 0x%llx\n", 86 HLS()->hart_id, HLS(), timecmp, when); /src/arch/riscv/mcall.c: 84 in mcall_set_timer() 78 79 uintptr_t mcall_set_timer(uint64_t when) 80 { 81 uint64_t *timecmp = HLS()->timecmp; 82 83 if (mcalldebug) >>> CID 1368527: (UNINIT) >>> Using uninitialized value "sp". 84 printk(BIOS_SPEW, 85 "hart %d: HLS %p: mcall timecmp@%p to 0x%llx\n", 86 HLS()->hart_id, HLS(), timecmp, when); 87 *timecmp = when; 88 clear_csr(mip, MIP_STIP); 89 set_csr(mie, MIP_MTIP); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] Native ram init panics linux kernel on samsung lumpy with CELERON 867 cpu.
by persmule 16 Jan '17

16 Jan '17

Hi all, The logs generated via "#cbmem -c" and "#inteltool -a" are attached accordingly. Best regards. Persmule 在 2017年01月16日 18:32, Kyösti Mälkki 写道: > On Mon, Jan 16, 2017 at 12:04 PM, Persmule <persmule(a)gmail.com> wrote: > >> Hi all, >> >> Recently I bought a second hand samsung lumpy >> (https://www.chromium.org/chromium-os/developer-information-for-chrome-os- >> devices/samsung-sandy-bridge) >> with CELERON 867 cpu, and tried to build a coreboot image with seabios >> in order to use this chromebook as an ordinary PC laptop running GNU/Linux. >> >> It seems that native ram init works on lumpies with core i5 cpu, but on >> mine, coreboot built with native ram init can run payloads with no >> problem, but linux kernel will panic with outputs showed on the attached >> photo (related to processors' synchronization?). Now I have to use Intel >> FSP to perform ram init, on which linux >> kernel (and GNU/Linux) works fine. >> >> > Just to clarify, the raminit blob for samsung/lumpy is not technically > Intel FSP, but different (MRC) blob created at Google. > > >> Config files for FSP and native ram init are also attached. >> >> > Please send output of cbmem -c and inteltool -a once system has booted with > raminit blob. > > >> Best regards. >> >> Persmule >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >>

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Native ram init panics linux kernel on samsung lumpy with CELERON 867 cpu.
by Persmule 16 Jan '17

16 Jan '17

Hi all, Recently I bought a second hand samsung lumpy (https://www.chromium.org/chromium-os/developer-information-for-chrome-os-de…) with CELERON 867 cpu, and tried to build a coreboot image with seabios in order to use this chromebook as an ordinary PC laptop running GNU/Linux. It seems that native ram init works on lumpies with core i5 cpu, but on mine, coreboot built with native ram init can run payloads with no problem, but linux kernel will panic with outputs showed on the attached photo (related to processors' synchronization?). Now I have to use Intel FSP to perform ram init, on which linux kernel (and GNU/Linux) works fine. Config files for FSP and native ram init are also attached. Best regards. Persmule

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Re: [coreboot] SMBIOS table enablement in coreboot
by Mayuri Tendulkar 16 Jan '17

16 Jan '17

Hi David Yes, below are settings for our system. As we are using Intel Baytrail, does this SMBIOS manufacturer shd be Intel? CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="xxxxx" # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="yyyy" Regards Mayuri From: David Hendricks [mailto:dhendrix@google.com] Sent: 14 January 2017 08:19 To: Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com> Cc: coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] SMBIOS table enablement in coreboot Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar <mayuri.tendulkar(a)aricent.com<mailto:mayuri.tendulkar@aricent.com>> wrote: Hi We are using coreboot for our board based on Intel Baytrail 3845. When we use dmidecode –t to get DDR details, we get empty. It means data is missing in SMBIOS. Are there any settings in coreboot to enable this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus." -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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Re: [coreboot] How to understand register address on x86?
by Alexander Böcken 16 Jan '17

16 Jan '17

Hello, this is a PCI related notation. It means Bus 0, Device 1-4, Function 0 of your board’s PCI bus. Then register offset 0x54, bits 31 to 19. Regards, Alex Von: coreboot [mailto:coreboot-bounces@coreboot.org] Im Auftrag von ??? Gesendet: Freitag, 13. Januar 2017 07:35 An: coreboot Betreff: [coreboot] How to understand register address on x86? Dear Sir. This time, I try to read the "V2_Avoton_BWG_Rev1_6_review.pdf" Page 169. Is see below. [cid:image001.jpg@01D26D74.F2F9B250] But I don't understand the SLOTCAP address (B0:D1-4:F0:Offset 0x54[31:19]). Could you explain this mean to me? Thank you.

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Re: [coreboot] Using as default external monitor for booting in x230
by Nico Huber 15 Jan '17

15 Jan '17

Hi, On 15.01.2017 01:12, Car.cuevas via coreboot wrote: > Hi, > > well actually, I will have to use Seabios as payload, since I may be > needing sometimes to boot to the windows which came pre-installed, but > 99% of times I am using Debian. And actually, my problem is about > using as default screen when booting the Bios, because of the FHD mod, > the screen which it should be used is the Digital 1 on Dock; the only > thing which can be found about this in the coreboot x230 code is: > > https://github.com/coreboot/coreboot/blob/master/src/mainboard/lenovo/x230/… > > (register "gpu_panel_port_select" = "0" # LVDS) I'm afraid this setting only affects panel power and backlight sequen- cing. > > So should I use there the value 2 or 3 as explained in > https://github.com/coreboot/coreboot/blob/master/src/northbridge/intel/sand… > ? It wouldn't matter as the current native gfx code in coreboot doesn't support external displays. I guess, the easiest option for your setup is to let SeaBIOS run the original Video BIOS with a modified VBT (I guess you already had to do something like that for the Lenovo BIOS?). If you want OSS for the gfx initialization, there's also libgfxinit (written in Ada, see 3rdparty/libgfxinit in the coreboot tree). It can enable external displays but would need some patching to make the panel power and backlight control work with that. Nico > > Thanks > > > > > > > > > -------- Original Message -------- Subject: Re: [coreboot] Using as > default external monitor for booting in x230 Local Time: January 14, > 2017 12:32 PM UTC Time: January 14, 2017 11:32 AM From: > mytbk920423(a)gmail.com To: coreboot(a)coreboot.org > > Hi, > > I've just flashed my X230 using Linux payload with petitboot. It can > light up the screen when the payload runs without any graphics init > (native gfx or VGA BIOS) in coreboot. > > My petitboot payload is built with the buildroot project from Arthur > Heymans[0]. I forked it and updated buildroot to a newer version. > > [0]: https://github.com/ArthurHeymans/petitboot_for_coreboot > > [1]: > https://github.com/mytbk/petitboot_for_coreboot/tree/buildroot-2016.11 > > Iru > > > On 2017年01月13日 20:46, Car.cuevas via coreboot wrote: >> >> Hi all, >> >> First thanks to all for such an amazing job, I just realized that >> Coreboot is already working in the lenovo x230, and I am really >> thinking in flash it and give a try :) But since I have a mod in my >> x230 for having FHD (edp screen), somehow I will need to somehow >> setup on the bios that I need to use the external Digital output (the >> one used for the dock station) as default... Is it any way to >> configure that? >> >> thanks very much in advance :) >> >> >> >> >> >> > > > -- coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] Using as default external monitor for booting in x230
by Iru Cai 15 Jan '17

15 Jan '17

Hi, I've just flashed my X230 using Linux payload with petitboot. It can light up the screen when the payload runs without any graphics init (native gfx or VGA BIOS) in coreboot. My petitboot payload is built with the buildroot project from Arthur Heymans[0]. I forked it and updated buildroot to a newer version. [0]: https://github.com/ArthurHeymans/petitboot_for_coreboot [1]: https://github.com/mytbk/petitboot_for_coreboot/tree/buildroot-2016.11 Iru On 2017年01月13日 20:46, Car.cuevas via coreboot wrote: > > Hi all, > > First thanks to all for such an amazing job, I just realized that > Coreboot is already working in the lenovo x230, and I am really > thinking in flash it and give a try :) But since I have a mod in my > x230 for having FHD (edp screen), somehow I will need to somehow setup > on the bios that I need to use the external Digital output (the one > used for the dock station) as default... Is it any way to configure that? > > thanks very much in advance :) > > > > > >

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Re: [coreboot] SMBIOS table enablement in coreboot
by David Hendricks 14 Jan '17

14 Jan '17

Hi Mayuri, Do you have GENERATE_SMBIOS_TABLES enabled in your config? On Fri, Jan 13, 2017 at 12:56 AM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi > > We are using coreboot for our board based on Intel Baytrail 3845. > > > > When we use *dmidecode –t *to get DDR details, we get empty. It means > data is missing in SMBIOS. > > > > Are there any settings in coreboot to enable this? > > > > Regards > > Mayuri > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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coreboot January 2017