coreboot January 2017

coreboot@coreboot.org

75 participants
186 discussions

Re: [coreboot] new problem with KGPE-d16
by Nico Huber 09 Jan '17

09 Jan '17

IIRC, https://review.coreboot.org/#/c/17910/ fixed something similar. It's merged yet, do you have it applied? Nico On 09.01.2017 23:27, David Hendricks via coreboot wrote: > Iru had a similar problem very recently: > https://www.coreboot.org/pipermail/coreboot/2017-January/082806.html > > Iru - Were you able to resolve the issue you saw? > > On Mon, Jan 9, 2017 at 2:13 PM, ron minnich <rminnich(a)gmail.com> wrote: >> what's weird is coreboot is unchanged, just the payload. >> >> I am wondering if anyone recognizes this >> >> IMD small region: >> IMD ROOT 0. bfffec00 00000400 >> ROMSTAGE 1. bfffebe0 00000004 >> GDT 2. bfffe9e0 00000200 >> Writing AMD DCT configuration to Flash >> CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) >> CBFS: Locating 's3nv' >> CBFS: Found @ offset 2fec0 size 10000 >> Manufacturer: ef >> SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 >> FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? >> SF: Failed to send command 06: 1 >> FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? >> SF: Failed to send command 06: 1 >> >> Also ... "Too much to write" ... I'll submit a CL but, folks, "Too much to >> write"? How about some numbers on this kind of message :-) >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > > >

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Re: [coreboot] new problem with KGPE-d16
by David Hendricks 09 Jan '17

09 Jan '17

Iru had a similar problem very recently: https://www.coreboot.org/pipermail/coreboot/2017-January/082806.html Iru - Were you able to resolve the issue you saw? On Mon, Jan 9, 2017 at 2:13 PM, ron minnich <rminnich(a)gmail.com> wrote: > what's weird is coreboot is unchanged, just the payload. > > I am wondering if anyone recognizes this > > IMD small region: > IMD ROOT 0. bfffec00 00000400 > ROMSTAGE 1. bfffebe0 00000004 > GDT 2. bfffe9e0 00000200 > Writing AMD DCT configuration to Flash > CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) > CBFS: Locating 's3nv' > CBFS: Found @ offset 2fec0 size 10000 > Manufacturer: ef > SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 > FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? > SF: Failed to send command 06: 1 > FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? > SF: Failed to send command 06: 1 > > Also ... "Too much to write" ... I'll submit a CL but, folks, "Too much to > write"? How about some numbers on this kind of message :-) > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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new problem with KGPE-d16
by ron minnich 09 Jan '17

09 Jan '17

what's weird is coreboot is unchanged, just the payload. I am wondering if anyone recognizes this IMD small region: IMD ROOT 0. bfffec00 00000400 ROMSTAGE 1. bfffebe0 00000004 GDT 2. bfffe9e0 00000200 Writing AMD DCT configuration to Flash CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 Manufacturer: ef SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? SF: Failed to send command 06: 1 FCH SPI: Too much to write. Does your SPI chip driver use spi_crop_chunk()? SF: Failed to send command 06: 1 Also ... "Too much to write" ... I'll submit a CL but, folks, "Too much to write"? How about some numbers on this kind of message :-)

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Re: [coreboot] Does the Core2Quad Mobile Q9100 require microcode updates?
by Timothy Pearson 09 Jan '17

09 Jan '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/09/2017 11:36 AM, ron minnich wrote: > > > On Mon, Jan 9, 2017 at 8:23 AM Taiidan(a)gmx.com <mailto:Taiidan@gmx.com> > <Taiidan(a)gmx.com <mailto:Taiidan@gmx.com>> wrote: > > On 01/08/2017 06:50 PM, Daniel Kulesz via coreboot wrote: > > > Hi, > > > > for the record: I had the Q9000 (not Q9100) running in my Thinkpad > T500 for a few weeks now without microcode updates and did not > encounter any issues so far. > > > absence of proof is not proof of absence. > I would personally be very wary of running Intel CPUs without microcode updates. Intel relies heavily on that "patch after ship" feature to iron out serious bugs (i.e. privilege escalation) in their hardware. - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYc8sOAAoJEK+E3vEXDOFb/YwH/AqhMYlwtUsEAOVAg1dRmGss wld98lITvh9gRv2vDPUxNrA8S2rhV8gE6OyQLn8EskyTRMNl8Wts9HR9gVBgPDO2 +mk6CQTVbWy7CBT4MZmGsJfx61KT+5valJCvH63RVciLPIY4v97w2KVPn1FE7IqN AlCPBZDuxvVvBbRFKepygb9v75Nse6yGt1f7DHdwasAOnKGxEr+kSqMDjCNIM7D7 p4Sh5u8WzBT/3+fYm4jViskZrPhKdlo6LLQcggrlurPeAItvccm3acULGkE2FeRD +R/Y984vIaS+qlGfkh+Es8Xo4xbeXDJQzIruifN4unOD295txwsFdJ/muSXYpsk= =eXl1 -----END PGP SIGNATURE-----

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Trusting coreboot versus trusting the FSP
by Trammell Hudson 09 Jan '17

09 Jan '17

At 33c3 a question came up about "how can we trust and audit coreboot?" compared to things like the Intel Firmware Support Package (FSP). I'm relaying it to the list for discussion. The FSP is a x86 binary blob that has an init function that writes magic values to magic registers to bring up the mainboard, the DRAM controller and other devices in the SOC. Meanwhile, many of the coreboot mainboard_init() functions write magic values to magic registers to bring up the mainboard, the DRAM controller and attached devices. For example, x230/mainboard.c: static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; } Do we trust the coreboot version because the C is easier to read than disassembly of the FSP, even though there is about the same level of documentation? What can we do to improve the auditability of coreboot if we don't understand the security implications of these magic values? -- Trammell

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Re: [coreboot] coreboot on KGPE-D16 "boot-loops"
by ron minnich 09 Jan '17

09 Jan '17

I'd be curious to know if any ram you have works ... On Mon, Jan 9, 2017 at 10:34 AM Pi Van Den Cirkel <opdecirkel(a)gmail.com> wrote: > Hey Timothy, I provided log for two cases. > 1) With RAM: HMT42GR7CMR4C-G7 D8 AC - two modules, one module in slot A2 > The log is: https://paste.debian.net/hidden/83d4816c/ and repeats over > and over again starting at: > > coreboot-4.5-771-gf3e2679-dirty Fri Jan 6 20:33:58 UTC 2017 romstage > starting... > > 2) With RAM Module: Nanya 4GB 2Rx8 PC3-10600E-9-10-E0 1333 ECC > (NT4GC72B8PG0NF-CG) > The boot process blockes at: ```ERROR: PNP: 002e.b 70 irq size: > 0x0000000001 not assigned``` > Full log: https://paste.debian.net/hidden/d38ffc04/ > > Let me know if you want me to enable extra logging. > > Thank you for helping! > > Another one with: > > On Mon, Jan 9, 2017 at 11:42 AM, Timothy Pearson > <tpearson(a)raptorengineering.com> wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > > > On 01/09/2017 10:27 AM, Taiidan(a)gmx.com wrote: > >> I don't know if this is the same problem as I lack a null modem cable > >> but mine sometimes takes 30 seconds or so to actually boot and show vga > >> output. > >> > >> If I flip the power switch and turn it back on after a little while I > >> have to wait much longer, in the meantime the PWM fans are off and it is > >> dead to the world. > >> > >> There is also a problem where loading the kernel too fast results in an > >> immediate reboot, I must wait at the grub screen for 15 seconds or so if > >> I don't want this to happen > >> > >> > >> I am curious do you guys have a uniprocessor system without the second > >> 8pin connection? > >> > > > > Could I get full coreboot serial boot logs from both of these machines? > > Without the logs I would just be guessing. > > > > Thanks! > > > > - -- > > Timothy Pearson > > Raptor Engineering > > +1 (415) 727-8645 <(415)%20727-8645> (direct line) > > +1 (512) 690-0200 <(512)%20690-0200> (switchboard) > > https://www.raptorengineering.com > > -----BEGIN PGP SIGNATURE----- > > Version: GnuPG v1 > > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ > > > > iQEcBAEBAgAGBQJYc71pAAoJEK+E3vEXDOFby+gH/3fcHF3FdnSYklKTyjURqc8L > > DXfIMyLQrBmMZKPcTFqBEriWyIon4qXEZJ/1lshO+7gjMLmk+Q2QC/Kjc7hux2Z1 > > gEzfalAUX8L+nhtEQJI3CtyX2GhiIj2oC7uifAlthcI/DAwoK52UQtdfDcJ8pSh4 > > iBLDgS6XK22i+NgUvDare41sAp8Ibg+emOA8CQ2azl/CYIQv9x1MrU8T8e9j/3mt > > 7bBPRZ1UrlT3rqy6a1kp/cA1CnyW4JkiAaVq7v+sZfc/CTAPdDf3Bb0/Te07//yg > > n6JbsQsh6IVqFCjlt6eM54xMD/aNCrVd9bbXKjyFBYJtTx0t8UDglXmVPepg8l4= > > =nxZ6 > > -----END PGP SIGNATURE----- > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] coreboot on KGPE-D16 "boot-loops"
by Taiidan＠gmx.com 09 Jan '17

09 Jan '17

I don't know if this is the same problem as I lack a null modem cable but mine sometimes takes 30 seconds or so to actually boot and show vga output. If I flip the power switch and turn it back on after a little while I have to wait much longer, in the meantime the PWM fans are off and it is dead to the world. There is also a problem where loading the kernel too fast results in an immediate reboot, I must wait at the grub screen for 15 seconds or so if I don't want this to happen I am curious do you guys have a uniprocessor system without the second 8pin connection?

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Re: [coreboot] Does the Core2Quad Mobile Q9100 require microcode updates?
by Daniel Kulesz 09 Jan '17

09 Jan '17

Hi, for the record: I had the Q9000 (not Q9100) running in my Thinkpad T500 for a few weeks now without microcode updates and did not encounter any issues so far. Cheers, Daniel On Sat, 12 Nov 2016 12:25:18 -0500 "Taiidan(a)gmx.com" <Taiidan(a)gmx.com> wrote: > It varies as per CPU revision, some have newer/older onboard microcode > than others. > > You won't know until you try it, or someone else with the exact same cpu > model/revision posts back (might take a long time) > > I would check the errata spec sheet to see if there is anything bad that > is addressed by later microcode updates post-your cpus onboard version. > On 11/12/2016 07:12 AM, Daniel Kulesz via coreboot wrote: > > Hi, > > > > I am considering upgrading my Coreboot'ing Thinkpad T500 with a Core2Quad Mobile Q9100 [1] (which requires some hardware modifications but is doable). My question is: Does this CPU require the microcode updates or will it run without? Practical experience from someone running this or a simular CPU from the same family (Q9000, Q9300) would be appreciated! > > > > Cheers, Daniel > > > > [1] http://ark.intel.com/products/37033/Intel-Core2-Quad-Processor-Q9100-12M-Ca… > > >

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Re: [coreboot] Trusting coreboot versus trusting the FSP
by Timothy Pearson 09 Jan '17

09 Jan '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 01/09/2017 11:10 AM, ron minnich wrote: > well, my flippant answer is also I think the right one: I don't see a > way to build a system I'd trust based on x86 or ARM CPUs any more, and > that's why I'm putting all my work into riscv. RISCV is not real, yet, > but it's getting there, and the x86 situation has only gotten worse, not > better, in the last dozen years :-( > > For reasons I don't quite understand, ARM Inc. has decided the x86 model > is the right one for ARM v8, and are diving into the UEFI/ACPII tarpit > just as deep as they can. I don't understand their thinking. > > I don't expect any of this to change; I expect it to get worse. And > riscv is no guarantee, either: there are some things built into that > architecture that can support vendor mischief, the main one being the > requirement to do BIOS calls to do trivial operations, such as enable > and reset timer interrupts, or find out your core id. Further, vendors > like Red Hat are pushing hard for UEFI and I assume ACPI as the RISCV > standard, for reasons I still don't understand. But it ought to be > possible to build RISCV systems that are much more trustworthy than the > x86/ARM systems. > > ron > POWER systems are also a good option for when RISC-V just won't get the job done (e.g. any kind of development work). The POWER8 SBE and microcode are now open source, and POWER9 will be even more transparent. - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJYc8dIAAoJEK+E3vEXDOFbApcIAIyUHseNPMtjbV4+bJGn7UGY l2K1jHSchfKGrIfOQhY7i4xoWY8MLfS+KW2hOf+9mTnZjuhaPEEjA+fRAXxIwCyL 8bAlFhvkkzI0Mh5YNSEKGp7VdqmGyldGeAF4+sfD0ktf+54Fqqv/N+/d/ExsDBSa Ur2M5jQ/VAIsBFCKUzjyW3KC06Y9GdGi922jcuDfTirvOtpHZ0iYtYbb8upDLoGr HoB/suuI53GDO0SPqSOG41T6oA00GVLQQH29ltyow5p7xH3QNBqgvJ0P9MfLO6k8 aeXsflnl8/oV3eMbX+hC35RZaIiQHO0GqcydXRbbHaS92nH0IDmibbKowJnyevg= =NF6Z -----END PGP SIGNATURE-----

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Minifree Libreboot D16 server/workstation launched
by Leah Rowe 09 Jan '17

09 Jan '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Hi all, Minifree has launched a new freedom-friendly computer. Two, in fact. Desktop/workstation version: https://minifree.org/product/libreboot-d16/ Server version: https://minifree.org/product/libreboot-d16-server/ This is a high-end AMD server platform, being sold in server and extended ATX (desktop/workstation) form factor. It comes with Debian and Libreboot preinstalled. This is the first modern commercial system available today that can be configured to run entirely free software; first Debian, the OS, and then libreboot, a free/libre BIOS implementation. With Debian and Libreboot, this is a fully free system containing zero binary blobs of any kind. This has positive implications for security in terms of audability, and therefore privacy in general (no backdoors!). It's also free software friendly, so there are zero binary blobs and zero proprietary software running on it in the OS or BIOS. You have all of the four freedoms over each part of the boot process, which means that you the user are in full control. For the first time ever, it is possible for companies to use libreboot-enabled hardware. The problem so far with Libreboot and Minifree is that it only focussed on low-end hardware. The launch of the D16 Server and D16 Desktop changes that. With this hardware you can: * do actual, serious work e.g. programming or 3D modeling. Software development nowadays requires powerful computers, because software becomes more complex. The sheer amount of time to build from source can be a problem on its own. The D16 can support up to 16 fast AMD Opteron cores per CPU, and 2 CPUs are possible so 32 cores in total. This is ideal for software development. * provide professional hosting services for paying clients, and run a small ISP * provide servers inside organisations * play modern games (libre ones) * etc (anything that requires a fast computer, basically) Spread the word! - -- Leah Rowe Libreboot developer Use free software. Free as in freedom. https://en.wikipedia.org/wiki/Free_software Use a free operating system, GNU+Linux. https://libreboot.org/docs/distros/ Or BSD: https://libreboot.org/docs/bsd/ Use a free BIOS. https://libreboot.org/ Support computer user freedom. https://peers.community/ Minifree Ltd, trading as Ministry of Freedom | Registered in England, No. 9361826 | VAT No. GB202190462 Registered Office: 19 Hilton Road, Canvey Island, Essex SS8 9QA, UK | Web: https://minifree.org/ -----BEGIN PGP SIGNATURE----- iQEcBAEBCAAGBQJYZmzjAAoJEP9Ft0z50c+UEikIAIITYZYamKacnYffR9Tw1VGA 2c4qD9u2hiAZb9/9CEaF0sFd6Z0GQdxfbvCWccBQqoR9WVa27jPUW7MgFm+wXYlJ r7nPm3q4MxWodHKFUdu/3mzxH7W/W1QUeCOoqXRHe2uUHoWT/pID/eXrhbjo62ZP Cuci4mMTHBrHt81nwQ+nO5COJXMJDVGs1h9RpJjbhKiyZP0lVIe4mD4ZNgu8eCI2 FW5dJS4NS8i63Zu3B8hCkHEvYE2pdiEBUraHmlUu57L8rxI9rM4kFFChFYvoNZnp Sl+mGfPk3GQPH009DzsaekEj44C1/zKGNbPAj3t1telRCu1Ffh0poWhzxuChrFU= =Cnub -----END PGP SIGNATURE-----

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coreboot January 2017