coreboot July 2016

coreboot@coreboot.org

47 participants
135 discussions

Re: [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed
by Zoran Stojsavljevic 04 Jul '16

04 Jul '16

Hello Werner, Could be that you are correct. I know that INTEL PED team themselves up-streamed the whole BDW-DE Coreboot code into Coreboot. Here is the pointer proving that: https://www.coreboot.org/pipermail/coreboot-gerrit/2016-April/042490.html +config CPU_MICROCODE_HEADER_FILES + string + default "../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h" The same I found in Jim's Coreboot config files: # CONFIG_BUILD_WITH_FAKE_IFD is not set CONFIG_TTYS0_BASE=0x3f8 CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h" CONFIG_FSP_LOC=0xffeb0000 CONFIG_SOC_INTEL_FSP_BROADWELL_DE=y York (Yang) is the one who can precisely answer on these questions. and maybe provide the latest MCUs, or at least these could be used for googlthe more recent BDX-DE MCUs. Also, BDX-DE CPUID is important (I think for CPUIDs 0x50661, 0x50662, 0x50663 and assuming also 0x50664), so for different CPUIDs different MCU updates should be used (not 100% sure, thought). Best Regards, Zoran On Mon, Jul 4, 2016 at 12:39 PM, Zeh, Werner <werner.zeh(a)siemens.com> wrote: > Hi Jim. > > > > According to the Postcode it seems like you have no valid microcode for > the used CPU. > > In src/drivers/intel/fsp1_0/cache_as_ram.inc is the code which ends up in > the endless loop while this code is shown. > > > > Check which CPU you really use on your mainboard and add the right > microcode to you configuration. > > This should solve your issue. > > > > Werner > > > > *Von:* coreboot [mailto:coreboot-bounces@coreboot.org] *Im Auftrag von * > ??? > *Gesendet:* Freitag, 1. Juli 2016 05:46 > *An:* coreboot(a)coreboot.org > *Betreff:* [coreboot] Bring up Intel Camelback Mountain Board with > coreboot+FSP failed > > > > Dear Sir, > > > > I just clone the latest coreboot source code from GIT > <http://review.coreboot.org/p/coreboot> and FSP from Intel FSP website > <https://downloadcenter.intel.com/download/25701>. > > Using " make crossgcc-i386 CPU=4 " to setup the compilation environment. > > But the Camelback Mountain board could not bring up successfully, > > it always hang with POST CODE = *0xCE*. > > From the Intel FSP spec 1.0, it seems that system halt before loading FSP. > > Attached is my .config file, is there anyone hit the fail symptoms same as > me and any idea to solve it? > > > > Thanks a lot, > > Jim > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed
by Zeh, Werner 04 Jul '16

04 Jul '16

Hi Jim. According to the Postcode it seems like you have no valid microcode for the used CPU. In src/drivers/intel/fsp1_0/cache_as_ram.inc is the code which ends up in the endless loop while this code is shown. Check which CPU you really use on your mainboard and add the right microcode to you configuration. This should solve your issue. Werner Von: coreboot [mailto:coreboot-bounces@coreboot.org] Im Auftrag von ??? Gesendet: Freitag, 1. Juli 2016 05:46 An: coreboot(a)coreboot.org Betreff: [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed Dear Sir, I just clone the latest coreboot source code from GIT<http://review.coreboot.org/p/coreboot> and FSP from Intel FSP website<https://downloadcenter.intel.com/download/25701>. Using " make crossgcc-i386 CPU=4 " to setup the compilation environment. But the Camelback Mountain board could not bring up successfully, it always hang with POST CODE = 0xCE. From the Intel FSP spec 1.0, it seems that system halt before loading FSP. Attached is my .config file, is there anyone hit the fail symptoms same as me and any idea to solve it? Thanks a lot, Jim

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Bring up Intel Camelback Mountain Board with coreboot+FSP failed
by 詹皓鈞 01 Jul '16

01 Jul '16

Dear Sir, I just clone the latest coreboot source code from GIT <http://review.coreboot.org/p/coreboot> and FSP from Intel FSP website <https://downloadcenter.intel.com/download/25701>. Using " make crossgcc-i386 CPU=4 " to setup the compilation environment. But the Camelback Mountain board could not bring up successfully, it always hang with POST CODE = *0xCE*. >From the Intel FSP spec 1.0, it seems that system halt before loading FSP. Attached is my .config file, is there anyone hit the fail symptoms same as me and any idea to solve it? Thanks a lot, Jim

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Re: [coreboot] Project for thesis
by Rafael Machado 01 Jul '16

01 Jul '16

Just a correction. Costa Rica is Central America guys :) Em qui, 30 de jun de 2016 às 21:07, Rafael Machado < rafaelrodrigues.machado(a)gmail.com> escreveu: > Hi Sergio > > Nice to see more people from South America here (I'm from Brazil). > > I don't have so much experience with coreboot like other guys here, but I > believe you could port coreboot to some platform that is still not > supported. > What do you think ? > Just remember that this may take from some hours to months, since you > probably have a target date. > > Maybe someone here have other ideas. > > Thanks and Regards > Rafael R. Machado > > > Em ter, 28 de jun de 2016 às 02:54, Sergio Valverde <valverde791(a)gmail.com> > escreveu: > >> Hello: >> >> My name is Sergio Valverde and I'm a student at Universidad de Costa >> Rica. I came across Google Summer of Code and I'm very interested in >> collaborating with you if any project of those is still available. I'm >> eager to participate in an open source project, especially one that >> involves Linux device drivers and Kernel hacking. >> >> I'm currently finishing my licentiate ("licenciatura") degree, which >> would be a degree between bachelor and master here in Costa Rica. For >> graduation, it requires a bachelor-level thesis, so I wanted to know if you >> have a project that has that kind of scope (or if I can propose one) and if >> it would be available for a student like me to collaborate. >> >> My background is in electronic engineering and I'm currently working as >> an embedded software developer in Hewlett Packard Enterprise in Costa Rica. >> I'm working in a SDK team for a networking ASIC and my main duties have >> involved building firmware images with Yocto, writing Linux device drivers >> for PCIe and coding software to interface high-level functions with >> hardware registers. >> >> I'm really looking forward for whatever information you can give me in >> this matter. I attached my resume to this mail and my Linkedin profile URL >> is https://cr.linkedin.com/in/sergio-valverde-9058b971. >> >> Hopefully we can work together. >> Sergio Valverde >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Project for thesis
by Rafael Machado 01 Jul '16

01 Jul '16

Hi Sergio Nice to see more people from South America here (I'm from Brazil). I don't have so much experience with coreboot like other guys here, but I believe you could port coreboot to some platform that is still not supported. What do you think ? Just remember that this may take from some hours to months, since you probably have a target date. Maybe someone here have other ideas. Thanks and Regards Rafael R. Machado Em ter, 28 de jun de 2016 às 02:54, Sergio Valverde <valverde791(a)gmail.com> escreveu: > Hello: > > My name is Sergio Valverde and I'm a student at Universidad de Costa Rica. > I came across Google Summer of Code and I'm very interested in > collaborating with you if any project of those is still available. I'm > eager to participate in an open source project, especially one that > involves Linux device drivers and Kernel hacking. > > I'm currently finishing my licentiate ("licenciatura") degree, which would > be a degree between bachelor and master here in Costa Rica. For graduation, > it requires a bachelor-level thesis, so I wanted to know if you have a > project that has that kind of scope (or if I can propose one) and if it > would be available for a student like me to collaborate. > > My background is in electronic engineering and I'm currently working as an > embedded software developer in Hewlett Packard Enterprise in Costa Rica. > I'm working in a SDK team for a networking ASIC and my main duties have > involved building firmware images with Yocto, writing Linux device drivers > for PCIe and coding software to interface high-level functions with > hardware registers. > > I'm really looking forward for whatever information you can give me in > this matter. I attached my resume to this mail and my Linkedin profile URL > is https://cr.linkedin.com/in/sergio-valverde-9058b971. > > Hopefully we can work together. > Sergio Valverde > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

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coreboot July 2016