coreboot November 2016

coreboot@coreboot.org

66 participants
187 discussions

Anyone have a experence the u-boot on coreboot?(Rangeley platform)
by 김유석 23 Nov '16

23 Nov '16

Dear Sir. My ENV is see below. CPU : Rangeley C2358(Based on ADI board) Curently, I'm try to use the u-boot(2016.05) but have a "boot fail". log is see below. U-Boot 2016.05-rc3 (Nov 23 2016 - 16:42:44 +0900) CPU: x86_64, vendor Intel, device 406d8h DRAM: 4 GiB dm_pci_hose_probe_bus: Internal error, bus 'pch@1,0' got seq 0, expected 1 Using default environment Model: QEMU x86 (I440FX) dm_pci_hose_probe_bus: Internal error, bus 'pch@1,0' got seq 0, expected 1 initcall sequence 7fc5a340 failed at call 01110185 (err=-32) ### ERROR ### Please RESET the board ### I was use the "qemu-x86_i440fx.dts" It is a default dts of u-boot. Boot failure is caused by "wrong DTS", I guess. And. A few month ago, I was success booted use the u-boot. But, I was lost the source code and memories.. Please advise to me. Thank you.

1 0

Re: [coreboot] Nehalem not booting with two ram sticks
by Charlotte Plusplus 23 Nov '16

23 Nov '16

Hello On Tue, Nov 22, 2016 at 4:28 PM, Zoran Stojsavljevic < zoran.stojsavljevic(a)gmail.com> wrote: > If MCU is later, could you, please, explain how you did this in IVB > Coreboot code (since this might be beneficial to Federico's attempts)? > Edit devicetree.cb and set: register "max_mem_clock_mhz" = "666" Here I understood that you tried to compare IVB raminit.c source code with > MRC algorithm, embedded in BIOS itself. And I have here one ignorant > question: what is the difference between IVB (I assumed in this case SNB > (tock), since I could not find IVB (tick) in rc/northbridge/intel/) > raminit.c source code and MRC from IVB BIOS (there MUST be some difference, > it is obvious, doesn't it)? > I suppose there is one. I don't know. I want to investigate. I will certainly try again by adding the patches suggested by Kyosti. As soon as I can get the MRC blob to work, I can make some better guesses about what is going wrong (I tried so many various things already) by having some reference points. At the moment, I want to make a first public commit for the W520, but with the RAM issues (only stable with the MCU at 666), and no native video init, and the power consumption issues, I'm not sure how helpful it will be. For the video init, the most plausible course of action is to see how the timings of the existing hardware initialization differ from say Xorg or the Linux Kernel, since the clock code is different and was found to be wrong on another patch. I'm glad I have examples. We don't have that with raminit. This is exactly the main point! And the main question here is the > following: who wrote raminit.c code, and does this person did it using > parts of IVB/SNB MRC source code? In other words, was this person member of > SNB BIOS team from INTEL CCG? > It was made by 2 persons I think, based on some reverse work > > This is also a good point. I need clarification on the following:* > "...will mean the MRC will be added back as an option next to the native > raminit"*. Do you mean to have IVB/SNB MRC binary blob with defined APIs > to be used as alternative to IVB/SNB raminit.c, since I am certain INTEL > will not allow to have complete MRC added in Coreboot as source code (never > was, never will be)? > Yeah, the blob. I don't like blob, but I like to have the option of something that works if I need to investigate why something else is not working. Or just for an initial release.

1 0

Re: [coreboot] Nehalem not booting with two ram sticks
by Charlotte Plusplus 23 Nov '16

23 Nov '16

Hello On Tue, Nov 22, 2016 at 2:50 PM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > >> I tried using the MRC blob to compare the timings, but I must have done >> something wrong in my code as it didn't work at all >> > > See following commits: > 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS > 0306e6a intel/sandybridge: Fix builds with System Agent blob > f9c4197 northbridge/sandybridge/raminit_mrc.c: fix missing include > Thanks, I keep an eye but I hadn't noticed them. I will try again the next few days. Was MRC blob ever really an option for lenovo/xxx boards? I did not check > history. > I have no idea. I just want to try and see if it can be made to work. Charlotte

1 0

Re: [coreboot] Nehalem not booting with two ram sticks
by Zoran Stojsavljevic 22 Nov '16

22 Nov '16

Hello Charlotte ++, Forgive me/apologies for my ignorance in some parts... I would like to ask few questions since I am not clear on some data here. On Tue, Nov 22, 2016 at 8:30 PM, Charlotte Plusplus < pluspluscharlotte(a)gmail.com> wrote: > I have had similar issues with Corsair ram on the W520 recently: sometimes > not booting at all, sometimes being unstable (in memest) after a succesfull > raminit. > > The only way I could get the 4 dimms to work was to hardcode some SPDs, or > set the MCU to a much slower speed. > As I know (and knew) MCU stands for MicroCode Unit (INTEL terminology), or Memory Controller Unit (common terminology), and I am sure you do refer to later, since to former this does not make too many (not at all) sense (to me, at least). If MCU is former, could you, please, explain the following: *"set the MCU to a much slower speed"*? If MCU is later, could you, please, explain how you did this in IVB Coreboot code (since this might be beneficial to Federico's attempts)? > Like you, I found removing even 1 stick did help a lot: the raminit > succeeded much more frequently as a higher MCU, even if this MCU still > lower than the one the RAM is rated for, or that worked in the factory bios. > > I tried using the MRC blob to compare the timings, but I must have done > something wrong in my code as it didn't work at all. > Here I understood that you tried to compare IVB raminit.c source code with MRC algorithm, embedded in BIOS itself. And I have here one ignorant question: what is the difference between IVB (I assumed in this case SNB (tock), since I could not find IVB (tick) in rc/northbridge/intel/) raminit.c source code and MRC from IVB BIOS (there MUST be some difference, it is obvious, doesn't it)? My guess is something is really wrong in the raminit code. I read up too > much specs and code for no result, so I just gave up on this. > This is exactly the main point! And the main question here is the following: who wrote raminit.c code, and does this person did it using parts of IVB/SNB MRC source code? In other words, was this person member of SNB BIOS team from INTEL CCG? This is much more question directed to INTEL people (IOTG and CCG) observing this thread. Also to Ron (Minnich). Or anybody else from Coreboot knowing the answer. Hopefully more people getting similar problems will mean the MRC will be > added back as an option next to the native raminit. This would facilite > comparison on all boards, and identification of whatever bug there may be. > (imagine figuring out native video init issues if there was no way to use a > VGA option rom) > This is also a good point. I need clarification on the following:* "...will mean the MRC will be added back as an option next to the native raminit"*. Do you mean to have IVB/SNB MRC binary blob with defined APIs to be used as alternative to IVB/SNB raminit.c, since I am certain INTEL will not allow to have complete MRC added in Coreboot as source code (never was, never will be)? Thank you (and everybody else) in advance for clarification (answers to these questions), Zoran Charlotte > > On Tue, Nov 22, 2016 at 8:22 AM, Andrey Korolyov <andrey(a)xdel.ru> wrote: > >> On Tue, Nov 22, 2016 at 3:35 PM, Federico Amedeo Izzo >> <federico.izzo42(a)gmail.com> wrote: >> > Hello, >> > >> > I have a problem with my ThinkPad X201 (nehalem) >> > >> > I have two sticks of Samsung 4GB 2Rx8 PC3-10600S (1333MHz) >> > When i use only one of them in one of the two slots, the computer boots >> > fine, >> > but when i use both of them in the two slots, the computer doesn't boot, >> > the screen doens't even turn on. >> > >> > I dumped the logs via EHCI but they seem normal, in fact both the >> > working combination and the broken one make 34 or so iterations of >> > Timings dumping, >> > but then the working conf. start booting, while the broken one freezes >> > without printing error messages on the EHCI. >> > >> > I have tried adding more `printk` calls in >> > `src/northbridge/intel/nehalem/raminit.c` >> > but ended up in a brick, probably because i slowed down the >> > initialization too much. >> > >> > I attach three EHCI logs: >> > - the first stick in the first slot: working >> > - the second stick in the second slot: working >> > - both stick inserted: not working >> > >> > Also i find difficult to understand the code in `raminit.c` of nehalem >> > because it lacks almost completely of comments, with respect to >> > raminit.c of sandybridge for example. >> >> I`ve seen simular issue on my x201(t), the workaround could be a >> hardcoded SPD limitation from above for memory clock speed. Using >> different memory sticks (Kingstons rather than Samsungs) is 'solving' >> problem as well. I`ve not paid necessary attention to the problem at >> the time, so if you have some spare cycles, you could possibly want to >> figure out right SPD settings. The simplest way is to use decode-dimms >> from i2c-tools or CPU-z and to compare vendor`s settings with single- >> and dual-dimm setups and coreboot`s with a single dimm. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] Nehalem not booting with two ram sticks
by Kyösti Mälkki 22 Nov '16

22 Nov '16

Hi On Tue, Nov 22, 2016 at 9:30 PM, Charlotte Plusplus < pluspluscharlotte(a)gmail.com> wrote: > I have had similar issues with Corsair ram on the W520 recently: sometimes > not booting at all, sometimes being unstable (in memest) after a succesfull > raminit. > > The only way I could get the 4 dimms to work was to hardcode some SPDs, or > set the MCU to a much slower speed. > > Like you, I found removing even 1 stick did help a lot: the raminit > succeeded much more frequently as a higher MCU, even if this MCU still > lower than the one the RAM is rated for, or that worked in the factory bios. > > I tried using the MRC blob to compare the timings, but I must have done > something wrong in my code as it didn't work at all > See following commits: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS 0306e6a intel/sandybridge: Fix builds with System Agent blob f9c4197 northbridge/sandybridge/raminit_mrc.c: fix missing include My guess is something is really wrong in the raminit code. I read up too > much specs and code for no result, so I just gave up on this. > > Hopefully more people getting similar problems will mean the MRC will be > added back as an option next to the native raminit. This would facilite > comparison on all boards, and identification of whatever bug there may be. > (imagine figuring out native video init issues if there was no way to use a > VGA option rom) > > Was MRC blob ever really an option for lenovo/xxx boards? I did not check history. Anyways, currently I have no trouble on samsung/lumpy changing between MRC and native raminits. And with native raminit it should now boot much faster than two weeks ago. Kyösti

1 0

Re: [coreboot] Nehalem not booting with two ram sticks
by Charlotte Plusplus 22 Nov '16

22 Nov '16

I have had similar issues with Corsair ram on the W520 recently: sometimes not booting at all, sometimes being unstable (in memest) after a succesfull raminit. The only way I could get the 4 dimms to work was to hardcode some SPDs, or set the MCU to a much slower speed. Like you, I found removing even 1 stick did help a lot: the raminit succeeded much more frequently as a higher MCU, even if this MCU still lower than the one the RAM is rated for, or that worked in the factory bios. I tried using the MRC blob to compare the timings, but I must have done something wrong in my code as it didn't work at all My guess is something is really wrong in the raminit code. I read up too much specs and code for no result, so I just gave up on this. Hopefully more people getting similar problems will mean the MRC will be added back as an option next to the native raminit. This would facilite comparison on all boards, and identification of whatever bug there may be. (imagine figuring out native video init issues if there was no way to use a VGA option rom) Charlotte On Tue, Nov 22, 2016 at 8:22 AM, Andrey Korolyov <andrey(a)xdel.ru> wrote: > On Tue, Nov 22, 2016 at 3:35 PM, Federico Amedeo Izzo > <federico.izzo42(a)gmail.com> wrote: > > Hello, > > > > I have a problem with my ThinkPad X201 (nehalem) > > > > I have two sticks of Samsung 4GB 2Rx8 PC3-10600S (1333MHz) > > When i use only one of them in one of the two slots, the computer boots > > fine, > > but when i use both of them in the two slots, the computer doesn't boot, > > the screen doens't even turn on. > > > > I dumped the logs via EHCI but they seem normal, in fact both the > > working combination and the broken one make 34 or so iterations of > > Timings dumping, > > but then the working conf. start booting, while the broken one freezes > > without printing error messages on the EHCI. > > > > I have tried adding more `printk` calls in > > `src/northbridge/intel/nehalem/raminit.c` > > but ended up in a brick, probably because i slowed down the > > initialization too much. > > > > I attach three EHCI logs: > > - the first stick in the first slot: working > > - the second stick in the second slot: working > > - both stick inserted: not working > > > > Also i find difficult to understand the code in `raminit.c` of nehalem > > because it lacks almost completely of comments, with respect to > > raminit.c of sandybridge for example. > > I`ve seen simular issue on my x201(t), the workaround could be a > hardcoded SPD limitation from above for memory clock speed. Using > different memory sticks (Kingstons rather than Samsungs) is 'solving' > problem as well. I`ve not paid necessary attention to the problem at > the time, so if you have some spare cycles, you could possibly want to > figure out right SPD settings. The simplest way is to use decode-dimms > from i2c-tools or CPU-z and to compare vendor`s settings with single- > and dual-dimm setups and coreboot`s with a single dimm. > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

1 0

Re: [coreboot] DMA protection? [AMD-Vi]
by Taiidan＠gmx.com 22 Nov '16

22 Nov '16

On 11/22/2016 12:48 AM, Zoran Stojsavljevic wrote: > Interesting thread. I would like to thank you to all for very/extremely > interesting read. And this thread forced me to start thinking/focusing > about these problems you have outlined here. > > I have no idea how things are handled in Coreboot regarding VT-x and VT-d. > I do know how these two HW extensions are handled in UEFI/legacy BIOS. You > either enable/disable them, independently, or not. So, if you, for example, > do not set VT-x, you are not able to bring any kind of HYP/VMMs, doing true > MMU xlation. The same applies for VT-d. If not set, not able to do any > IOMMU xlation. > > I tried to find in Coreboot 4.4 (from August 2016) both VT-x and VT-d > settings, but was not able to find any switches in .config. My question > here is: *how HW extensions for INTEL/AMD VT-x and VT-d are handled - > enabled/disabled in Coreboot?* > > Let me now switch to another part of this thread, main part: BME (Bus > Master Enable). This is a different topic, but related to VTs. I would > agree with Ron (Minnic) on his comment that minimum of the HW should be > configured in Coreboot, so my take on this is that BME should be NOT > enabled anyhow, anywhere, and left to actual OS to do this. Since Coreboot > is true Linux oriented, I would say that kernel should properly go over > PCIe discovery algorithm/PCIe tree discovered and set properly bridges with > BME (by configuring kernel .config). > > In this lieu, I would like to propose two addendums: one already proposed > by several people (Ron): to have added BME algorithm to ram-stage of > Coreboot, which will print warnings for any bridge which has BME bit set, > and other one: to create critical Bugzilla against Linus's (Torvalds) crew ( > kernel.org) to add proper handling of BMEs in kernel.org: > https://bugzilla.kernel.org/ . > > About security aspects... It is to be taken into the account *AFTER* > proposed changes (logical steps), since we divide and conquer, don't we? > > Thank you, > Zoran > > On Mon, Nov 21, 2016 at 10:15 PM, ron minnich <rminnic Yes! thank you to all for an excellent thread. It has been very informative. With a normal bios the gui simply sets CMOS settings, and in coreboot we currently have no gui so we must set them with "nvramcui" or in the cmos.defaults at compile time (file in the motherboard folder) coreboot/src/mainboard/asus/kgpe-d16 And here we set: iommu = Enable There however is not one for HVM as far as I can tell. I propose not referring to IOMMU as the intel branded "VT-d", I have encountered many people who think that it is an intel technology and that no other company has an equivalent (lol).

1 0

Nehalem not booting with two ram sticks
by Federico Amedeo Izzo 22 Nov '16

22 Nov '16

Hello, I have a problem with my ThinkPad X201 (nehalem) I have two sticks of Samsung 4GB 2Rx8 PC3-10600S (1333MHz) When i use only one of them in one of the two slots, the computer boots fine, but when i use both of them in the two slots, the computer doesn't boot, the screen doens't even turn on. I dumped the logs via EHCI but they seem normal, in fact both the working combination and the broken one make 34 or so iterations of Timings dumping, but then the working conf. start booting, while the broken one freezes without printing error messages on the EHCI. I have tried adding more `printk` calls in `src/northbridge/intel/nehalem/raminit.c` but ended up in a brick, probably because i slowed down the initialization too much. I attach three EHCI logs: - the first stick in the first slot: working - the second stick in the second slot: working - both stick inserted: not working Also i find difficult to understand the code in `raminit.c` of nehalem because it lacks almost completely of comments, with respect to raminit.c of sandybridge for example.

3 2

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 22 Nov '16

22 Nov '16

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 6 new defect(s) introduced to coreboot found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 6 of 6 defect(s) ** CID 1353028: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 341 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353028: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 341 in integrate_psp_firmwares() 335 pspdir[4+4*i+2] = 1; 336 pspdir[4+4*i+3] = 0; 337 } else if (fw_table[i].filename != NULL) { 338 pspdir[4+4*i+0] = fw_table[i].type; 339 340 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353028: Error handling issues (NEGATIVE_RETURNS) >>> "fd" is passed to a parameter that cannot be negative. [Note: The source code implementation of the function has been overridden by a builtin model.] 341 fstat(fd, &fd_stat); 342 pspdir[4+4*i+1] = (uint32_t)fd_stat.st_size; 343 344 pspdir[4+4*i+2] = pos + rom_base_address; 345 pspdir[4+4*i+3] = 0; 346 ** CID 1353027: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 284 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353027: Error handling issues (NEGATIVE_RETURNS) /util/amdfwtool/amdfwtool.c: 284 in integrate_firmwares() 278 int i; 279 uint32_t rom_base_address = 0xFFFFFFFF - rom_size + 1; 280 281 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { 282 if (fw_table[i].filename != NULL) { 283 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353027: Error handling issues (NEGATIVE_RETURNS) >>> "fd" is passed to a parameter that cannot be negative. [Note: The source code implementation of the function has been overridden by a builtin model.] 284 fstat(fd, &fd_stat); 285 286 switch (fw_table[i].type) { 287 case AMD_FW_IMC: 288 pos = ALIGN(pos, 0x10000U); 289 romsig[1] = pos + rom_base_address; ** CID 1353021: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 355 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353021: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 355 in integrate_psp_firmwares() 349 " will not fit %s. Exiting.\n", 350 rom_size, fw_table[i].filename); 351 free(base); 352 exit(1); 353 } 354 >>> CID 1353021: Error handling issues (CHECKED_RETURN) >>> "read(int, void *, size_t)" returns the number of bytes read, but it is ignored. 355 read(fd, (void *)(base + pos), (size_t)fd_stat.st_size); 356 357 pos += fd_stat.st_size; 358 close(fd); 359 pos = ALIGN(pos, 0x100U); 360 } else { ** CID 1353020: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 341 in integrate_psp_firmwares() ________________________________________________________________________________________________________ *** CID 1353020: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 341 in integrate_psp_firmwares() 335 pspdir[4+4*i+2] = 1; 336 pspdir[4+4*i+3] = 0; 337 } else if (fw_table[i].filename != NULL) { 338 pspdir[4+4*i+0] = fw_table[i].type; 339 340 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353020: Error handling issues (CHECKED_RETURN) >>> Calling "fstat(fd, &fd_stat)" without checking return value. This library function may fail and return an error code. [Note: The source code implementation of the function has been overridden by a builtin model.] 341 fstat(fd, &fd_stat); 342 pspdir[4+4*i+1] = (uint32_t)fd_stat.st_size; 343 344 pspdir[4+4*i+2] = pos + rom_base_address; 345 pspdir[4+4*i+3] = 0; 346 ** CID 1353019: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 310 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353019: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 310 in integrate_firmwares() 304 " will not fit %s. Exiting.\n", 305 rom_size, fw_table[i].filename); 306 free(base); 307 exit(1); 308 } 309 >>> CID 1353019: Error handling issues (CHECKED_RETURN) >>> "read(int, void *, size_t)" returns the number of bytes read, but it is ignored. 310 read(fd, (void *)(base + pos), (size_t)fd_stat.st_size); 311 312 pos += fd_stat.st_size; 313 close(fd); 314 pos = ALIGN(pos, 0x100U); 315 } ** CID 1353018: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 284 in integrate_firmwares() ________________________________________________________________________________________________________ *** CID 1353018: Error handling issues (CHECKED_RETURN) /util/amdfwtool/amdfwtool.c: 284 in integrate_firmwares() 278 int i; 279 uint32_t rom_base_address = 0xFFFFFFFF - rom_size + 1; 280 281 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) { 282 if (fw_table[i].filename != NULL) { 283 fd = open(fw_table[i].filename, O_RDONLY); >>> CID 1353018: Error handling issues (CHECKED_RETURN) >>> Calling "fstat(fd, &fd_stat)" without checking return value. This library function may fail and return an error code. [Note: The source code implementation of the function has been overridden by a builtin model.] 284 fstat(fd, &fd_stat); 285 286 switch (fw_table[i].type) { 287 case AMD_FW_IMC: 288 pos = ALIGN(pos, 0x10000U); 289 romsig[1] = pos + rom_base_address; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

How to read/write the spi flash on SeaBIOS?
by 김유석 22 Nov '16

22 Nov '16

Dear Sir. I want to read/write some data to spi flash on SeaBIOS. But i can't found some code or starting point. Do you have a IDEA? If you have a idea or experence, please advise to me. Thank you.

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
19
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2016