coreboot November 2016

coreboot@coreboot.org

66 participants
187 discussions

EC problem in X200s?
by Iru Cai 04 Nov '16

04 Nov '16

Hi, Recently, I flashed libreboot to my X200s (with L9300 CPU). But it seems that there are some EC problems in X200s, which I haven't found in a X200. 1. With a third party battery, when I put the X200s on dock, it'll shut down. 2. With a third party battery, the battery will not charge, but it can charge on a libreboot X200 or another X200s (with a single core Celeron CPU, not tested on the same X200s) with factory firmware. 3. At last I bought a factory battery, the first two problems will not appear. In these two days, I found that when I charge with a 90W adapter, the CPU will get very hot and the laptop will shut down. It seems that it'll not happen with a 65W adapter. Iru -- Please do not send me Microsoft Office/Apple iWork documents. Send OpenDocument instead! http://fsf.org/campaigns/opendocument/

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[Broadwell-DE] camelbackmountain_fsp project fail on USB initilalize
by James_Lee 03 Nov '16

03 Nov '16

Hello All, My platform is Intel camelback CRB, I use coreboot +intel FSP, BIOS can post to boot state, but on SeaBIOS init USB device have Happen initial time out issue, have some guys know the issue root Cause ? Thanks. Best Regards -James Scan for VGA option rom XHCI init on dev 00:14.0: regs @ 0xfea00000, 21 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 XHCI extcap 0xc1 @ fea08040 XHCI extcap 0xc0 @ fea08070 XHCI extcap 0x1 @ fea0846c WARNING - Timeout at i8042_flush:71! EHCI init on dev 00:1a.0 (regs=0xfea18020) Found 0 lpt ports Found 1 serial ports AHCI controller at 1f.2, iobase fea17000, irq 5 EHCI init on dev 00:1d.0 (regs=0xfea19020) XHCI no devices found Initialized USB HUB (0 ports used) WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef73380 cur=7ef6ce00 tok=00000d00 next=7ef6cdc0 td=0x7ef6cdc0 status=80e80 WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef72b80 cur=7ef6ee00 tok=00000c00 next=7ef4fd80 td=0x7ef4fd80 status=80e80 WARNING - Timeout at ehci_waittick:178! Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@3/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@3 WARNING - Timeout at ehci_waittick:165! Failure on hub port 0 detect WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x000eee80 cur=00000000 tok=00000000 next=7ef6ccc0 td=0x7ef6ccc0 status=1f0c80 WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef72b80 cur=7ef6ee00 tok=00000000 next=7ef6ed80 td=0x7ef6ed80 status=80e80 WARNING - Timeout at ehci_waittick:165! USB transmission failed Unable to configure USB MSC drive. Unable to configure USB MSC device. WARNING - Timeout at ehci_waittick:165! Failure on hub port 3 reset WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef72b80 cur=7ef6ee00 tok=00000000 next=7ef6ed80 td=0x7ef6ed80 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 3 disconnect WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef72b80 cur=7ef6ee00 tok=00000000 next=7ef6cdc0 td=0x7ef6cdc0 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 2 disconnect WARNING - Timeout at ehci_wait_td:515! ehci pipe=0x7ef72b80 cur=7ef6ee00 tok=00000000 next=7ef4ed80 td=0x7ef4ed80 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 1 detect Initialized USB HUB (0 ports used) WARNING - Timeout at ehci_waittick:165! All threads complete. Scan for option roms

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Unknown POSTcodes and Normalcy Questions
by Haleigh Novak 03 Nov '16

03 Nov '16

Hello All, I was able to read the postcodes from coreboot on a successful Centos6.7 boot so I could see what they were; I have found all of them defined within the code except: 69, 3C, and B5. From googling 69 seems to have something to do with incorrect or dead ram but the other two I can not seem to locate at all. Does anyone know what these three codes are defined as or where they would be / are? There are also three large postcode transmission chunks that are only code 00; their lengths are 9, 18, and 54 entries long - does anyone know if is this normal? Thank you for your time. HN

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Baytrail LPSS DMA's size in ACPI
by szr 02 Nov '16

02 Nov '16

Hello I can mistake, but, probably Baytrail LPSS DMA's size in soc/intel/fsp_baytrail/acpi/lpss.asl should be equal 0x4000 instead of 0x1000 now. That size appears in ...coreboot boot log: PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1e.0 PCI: 00:1e.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 ...acpi dump from Intel NUC 3815: DefinitionBlock ("", "DSDT", 2, "INTEL", "DE3815TY", 0x01072009) <...> Device (GDM1) { Name (_HID, "INTL9C60" /* Intel Baytrail SOC DMA Controller */) // _HID: Hardware ID Name (_DDN, "Intel(R) DMA Controller #1 - INTL9C60") // _DDN: DOS Device Name Name (_UID, One) // _UID: Unique ID Name (RBUF, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00004000, // Address Length _Y24) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) { 0x0000002A, } }) ...here: https://github.com/tianocore/edk2/blob/master/Vlv2DeviceRefCodePkg/AcpiTabl… --- Alex.

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Radare i946.bin
by Riko Ho 02 Nov '16

02 Nov '16

Everyone, Idwer... Here's what I've been playing with radare, bianchi@ubuntu:~/Documents/Coreboot Column$ r2 -e asm.bits=16 -e io.va=true i946gz_Edited.bin [f000:fff0]> b7 [f000:fff0]> pd ;-- entry0: f000:fff0 ea5be000f0 jmp word 0xf000:0xe05b f000:fff5 2a4d52 sub cl, [di+0x52] f000:fff8 42 inc dx f000:fff9 2a02 sub al, [bp+si] f000:fffb 0000 add [bx+si], al f000:fffd 0060ff add [bx+si-0x1], ah ;-- section_end.bootblk: where can I see the relation between that block with PCIEXBAR register ? Cheers,

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Petitboot based bootloader
by Arthur Heymans 02 Nov '16

02 Nov '16

Hi I have been working on building a Petitboot, a kexec bootloader, [0] based Linux payload using the Buildroot build system to produce a nice bzImage that contains both linux and the initrd. It is inspired by the Raptor Enginering HOWTO [0] and is based on op-build [1], the tool for building OpenPOWER firmware, which also uses Buildroot and Petitboot. One of the advantages of Petitboot is that it is fairly simple and intuitive to use and does not require complex configuration like grub does, while still providing a large range of hardware support since it uses linux at its core. A disadvantage is that a Linux + initrd payload takes up quite a bit of space. A fairly stripped down kernel + initrd takes up ~6.9M in the current Buildroot + Linux configuration I have. So a large flash chip or replacing the flash with a larger one is recommended. Coreboot can directly use this Linux payload or first load SeaBIOS which can then chainload the Linux payload. It is still very much a WIP and is currently aimed at Intel hardware, but with a kernel configuration tuned to your target it should work fine. The repo + initial documentation: https://github.com/ArthurHeymans/petitboot_for_coreboot [0] Petitboot: A kexec based bootloader, https://www.kernel.org/pub/linux/kernel/people/geoff/petitboot/petitboot.ht… [1] Creating firmware images with petitboot and coreboot https://secure.raptorengineering.com/content/kb/1.html [2] OpenPower Firmware Build Environment https://github.com/open-power/op-build Kind Regards -- Arthur Heymans

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PCIEXBAR 946 and 945
by Riko Ho 01 Nov '16

01 Nov '16

Good day everyone, I got info from Kmalkki, that I need to adapt PCIEXBAR value for 946 from 945 I saw in bootblock.c for 945, it's 0x48... What value is it for i946 ? I tried reading datasheet, I found it on page 43, page 55 and pointing to chapter 6, but I can not find a clear explaination on how to use PCIEXBAR register... Does anyone come to this point as well ? How to solve it ? If I can not get the right value, I don't think I can give a good initialization for my IT8718F, because I can not point the address for it.. Cheers

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coreboot November 2016