coreboot January 2016

coreboot@coreboot.org

38 participants
74 discussions

Building on 64 Bit Linux
by Gregg Levine 19 Jan '16

19 Jan '16

Hello! Is there anything special I need to know when it comes to building releases on a 64 Bit Linux system? This is Slackware64-14.1 as it happens. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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MbMax coreboot image
by Supriti Singh 19 Jan '16

19 Jan '16

I am trying to build coreboot image for MbMax along with TXE module I selected under menuconfig --> chipset --> Add Inteldescriptor.bin file --> Add Intel ME/TXE firmware. When I do a make, I get the error: DD Adding Intel Firmware Descriptor make: *** [add_intel_firmware] Error 1 I did a git clone http://review.coreboot.org/p/blobs.git to get the blobs. But it does not contain anything for MbMax. I followed the instructions here http://wiki.minnowboard.org/Coreboot. It explains to use ifdtool to extract TXE firmware image. Is this the image that should be present in the blobs/mainboard/intel/? If not how to get the it? Thanks, Supriti

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Re: [coreboot] cbfstool: CBFS alignment broken due to FMAP
by Zeh, Werner 19 Jan '16

19 Jan '16

Hi Ben. Alternatively you can use your own flash map setup file where you modify FMAP_FMAP_SIZE to your needs and point Kconfig to your modified fmd-file. In this way you can leave Makefile.inc unchanged and get your image right as well. Werner -----Ursprüngliche Nachricht----- Von: coreboot [mailto:coreboot-bounces@coreboot.org] Im Auftrag von Ben Gardner Gesendet: Montag, 18. Januar 2016 21:54 An: Patrick Georgi Cc: coreboot Betreff: Re: [coreboot] cbfstool: CBFS alignment broken due to FMAP Thank you. That worked. On Mon, Jan 18, 2016 at 2:46 PM, Patrick Georgi <pgeorgi(a)google.com> wrote: > 2016-01-18 21:34 GMT+01:00 Ben Gardner <gardner.ben(a)gmail.com>: >> Is there a work-around for this? For example, is there an option to >> pad the FMAP out to 4 KB? > The workaround is indeed to increase the FMAP region's size to 4K. > > To do this, edit $(top)/Makefile.inc, line 708 (since you're on x86, > otherwise line 723): > FMAP_FMAP_SIZE := 0x100 > to > FMAP_FMAP_SIZE := 0x1000 > > > Patrick > -- > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und > -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg > Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] cbfstool: CBFS alignment broken due to FMAP
by Ben Gardner 18 Jan '16

18 Jan '16

Thank you. That worked. On Mon, Jan 18, 2016 at 2:46 PM, Patrick Georgi <pgeorgi(a)google.com> wrote: > 2016-01-18 21:34 GMT+01:00 Ben Gardner <gardner.ben(a)gmail.com>: >> Is there a work-around for this? For example, is there an option to >> pad the FMAP out to 4 KB? > The workaround is indeed to increase the FMAP region's size to 4K. > > To do this, edit $(top)/Makefile.inc, line 708 (since you're on x86, > otherwise line 723): > FMAP_FMAP_SIZE := 0x100 > to > FMAP_FMAP_SIZE := 0x1000 > > > Patrick > -- > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg > Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg > Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Re: [coreboot] cbfstool: CBFS alignment broken due to FMAP
by Patrick Georgi 18 Jan '16

18 Jan '16

2016-01-18 21:34 GMT+01:00 Ben Gardner <gardner.ben(a)gmail.com>: > Is there a work-around for this? For example, is there an option to > pad the FMAP out to 4 KB? The workaround is indeed to increase the FMAP region's size to 4K. To do this, edit $(top)/Makefile.inc, line 708 (since you're on x86, otherwise line 723): FMAP_FMAP_SIZE := 0x100 to FMAP_FMAP_SIZE := 0x1000 Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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cbfstool: CBFS alignment broken due to FMAP
by Ben Gardner 18 Jan '16

18 Jan '16

Hi all, With the latest cbfstool in master, the alignment option is broken in cbfstool. Or rather, the alignment is relative to the CBFS start, not the actual ROM address, and the 256-byte FMAP throws off the alignment. In my case, I have a ROM size of 16 MB and the BIOS region starts at 0x200000. Layout from ifdtool (sorted): 00000000:00000fff fd 00001000:001fffff me 00200000:00ffffff bios Layout from cbfstool: 'BIOS' (read-only, size 14680064) 'FMAP' (read-only, size 256) 'COREBOOT' (CBFS, size 14679808) When I add a 16 KB file with alignment 4096: $ cbfstool coreboot.rom add -f 16kb_ff.bin -n alignment.bin -t raw -a 4096 The new file is aligned in the CBFS at 0x99000. $ cbfstool output/coreboot.rom print Performing operation on 'COREBOOT' region... Name Offset Type Size ... snip ... (empty) 0x98640 null 2392 alignment.bin 0x98fc0 raw 16384 (empty) 0x9d000 null 13774488 ... snip ... But due to the FMAP, that address is really 0x99100, not 0x99000, which is not 4 KB aligned. 002990c0 4c 41 52 43 48 49 56 45 00 00 40 00 00 00 00 50 |LARCHIVE..@....P| 002990d0 00 00 00 28 00 00 00 40 61 6c 69 67 6e 6d 65 6e |...(...@alignmen| 002990e0 74 2e 62 69 6e 00 00 00 42 43 5a 4c 00 00 00 10 |t.bin...BCZL....| 002990f0 00 00 00 00 00 00 40 00 ff ff ff ff ff ff ff ff |......@.........| 00299100 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| And this is because the CBFS starts at 0x2000100 instead of 0x2000000. Is there a work-around for this? For example, is there an option to pad the FMAP out to 4 KB? Or maybe a way to force the CBFS to be place at a 4 KB alignment? Is someone working on a patch? Thanks, Ben

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Re: [coreboot] steps before screen mods
by kitestramuort 18 Jan '16

18 Jan '16

> Hi guys, > > I just came across thinkpad forum thread where people are discuss about > hardware mods for getting FHD screen on lenovo x220/x230 laptops. > http://forum.thinkpads.com/viewtopic.php?f=43&t=106919&start=90 > > What do you guys think, will this affect coreboot at all? Are there any > necessary steps before playing with the screen? > Hi all, I was wondering whether there was any progress on this. I have a modded X230 and managed to patch the i915 kernel driver to disable LVDS and get my screen correctly detected as eDP using the stock uefi bios. The patch is attached. Now I am thinking of flashing coreboot, mainly to get rid of the dreadful wlan whitelist, but I am afraid of losing the functionality... Basically the mod consists of an interface board that rewires the dock DP port (DP-3, PORT_D) to the fhd panel. It would be great if we could patch coreboot to natively support the eDP FHD screen. I am not really an expert, all I could come up with was to change register "gpu_panel_port_select" = "0" with "3" (that should be DP_D) in mainboard/lenovo/x230/devicetree.cb but I don't think this will suffice at all... Here is my intel-gfx post for reference http://lists.freedesktop.org/archives/intel-gfx/2015-July/072787.html Best regards

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Will coreboot work on my Asus P5G41-M?
by Vicente Herrera Cobo 18 Jan '16

18 Jan '16

Hi, the FAQ explicitly asked to send information about currently unsupported motherboard. https://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F 1. Asus P5G41-M. Intel Core 2 Duo E7600 @ 3.06GHz. Northbridge G41. Southbridge ICH7. 2. lspci -tvnn. See lspci.txt attached. 3. Super I/O chip: Winbond W83627DHG-P/-PT. See superiotool.txt attached. 4. BIOS: Winbond flash chip "W25X80" (1024 kB, SPI). See flashroom.txt 5. https://www.asus.com/Motherboards/P5G41M/specifications/ http://dlcdnet.asus.com/pub/ASUS/mb/socket775/P5G41-M/E4832_P5G41-M-manual.… Thank you for your attention. Congratulations for your work, Vicente.

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Re: [coreboot] how to route IRQ4 (COM1) on LPC bus for bayleybay_fsp
by benoit 16 Jan '16

16 Jan '16

Everything works right now. I explained and tested it at http://www.coreboot.org/pipermail/coreboot/2016-January/080845.html FYI, I activated the SERIRQ in file src/soc/intel/fsp_baytrail/southcluster.c by defining SETUPSERIQ and CONFIG_SERIRQ_CONTINUOUS_MODE in my Kconfig in my mainboard folder. I can confirm that all the LPC stuffs are working well. (Accesses + IRQs) On 15/01/2016 20:49, Aaron Durbin wrote: > On Fri, Jan 15, 2016 at 1:44 PM, benoit <benoit.sansoni(a)gmail.com> wrote: >> Hi, >> >> As explained in my post, I am not using the UART located in the Baytrail >> SOC. >> I used an SIO for serial line connected to the LPC bus. >> So to have the IRQs of these serial lines, I obviuosly need to SERIRQ. >> The IRQEN is only for the COM1 located in the SOC. >> > > I missed that part about the SIO. In the past on a bay trail project > we couldn't use SERIRQ because the LPC device and bay trail didn't > support the same SERIRQ frame sequence -- thus badness all around. > Have scoped the SERIRQ lines at all? Maybe the LPC device isn't > asserting? Or maybe SERIRQ isn't running at all. > >> Thanks for your help >> Benoit >> >> On 14/01/2016 23:09, Aaron Durbin wrote: >>> On Tue, Jan 12, 2016 at 2:32 PM, benoit <benoit.sansoni(a)gmail.com> wrote: >>>> Hi all, >>>> >>>> I am currently running coreboot + fsp on a E3837 cpu based platform. >>>> My platform has serial line in a LPC device. >>>> Firstly, I activated the SERIRQ in continous mode. >>> >>> SERIRQ has nothing to do w/ COM1. SERIRQ is pulled in on LPC. >>> >>>> Nevertheless under operating system, the IRQ4 for COM1 is not available. >>> >>> IRQEN (IRQE)—Offset 88h bit 4 indicates UART IRQ4 Enable. The >>> datasheet says RO, but you could double check that it's RW. That sit >>> behind the ILB_BASE_ADDRESS. >>> >>> In the datasheet it's section 34.3.53. >>> http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e38… >>> >>>> >>>> I checked out the file src/mainboard/intel/bayleybay_fsp/irqtable.h >>>> And I saw that for the LPC interface : >>>> >>>> PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) >>>> ... >>>> #define PIRQ_PIC_ROUTES \ >>>> PIRQ_PIC(A, 4), \ >>>> PIRQ_PIC(B, 5), \ >>>> PIRQ_PIC(C, 7), \ >>>> PIRQ_PIC(D, 10), \ >>>> PIRQ_PIC(E, 11), \ >>>> PIRQ_PIC(F, 12), \ >>>> PIRQ_PIC(G, 14), \ >>>> PIRQ_PIC(H, 15) >>>> >>>> I know that this configuration is available from the ILB_BASE_ADDRESS >>>> (0xfed08000). >>>> But I don't really understand, how to route the IRQ4 from LPC dev. >>>> >>>> Is someone can explain to me how to do it properly? >>>> >>>> Many thanks in advance >>>> Benoit >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >

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Re: [coreboot] how to route IRQ4 (COM1) on LPC bus for bayleybay_fsp
by benoit 15 Jan '16

15 Jan '16

Hi, As explained in my post, I am not using the UART located in the Baytrail SOC. I used an SIO for serial line connected to the LPC bus. So to have the IRQs of these serial lines, I obviuosly need to SERIRQ. The IRQEN is only for the COM1 located in the SOC. Thanks for your help Benoit On 14/01/2016 23:09, Aaron Durbin wrote: > On Tue, Jan 12, 2016 at 2:32 PM, benoit <benoit.sansoni(a)gmail.com> wrote: >> Hi all, >> >> I am currently running coreboot + fsp on a E3837 cpu based platform. >> My platform has serial line in a LPC device. >> Firstly, I activated the SERIRQ in continous mode. > > SERIRQ has nothing to do w/ COM1. SERIRQ is pulled in on LPC. > >> Nevertheless under operating system, the IRQ4 for COM1 is not available. > > IRQEN (IRQE)—Offset 88h bit 4 indicates UART IRQ4 Enable. The > datasheet says RO, but you could double check that it's RW. That sit > behind the ILB_BASE_ADDRESS. > > In the datasheet it's section 34.3.53. > http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e38… > >> >> I checked out the file src/mainboard/intel/bayleybay_fsp/irqtable.h >> And I saw that for the LPC interface : >> >> PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) >> ... >> #define PIRQ_PIC_ROUTES \ >> PIRQ_PIC(A, 4), \ >> PIRQ_PIC(B, 5), \ >> PIRQ_PIC(C, 7), \ >> PIRQ_PIC(D, 10), \ >> PIRQ_PIC(E, 11), \ >> PIRQ_PIC(F, 12), \ >> PIRQ_PIC(G, 14), \ >> PIRQ_PIC(H, 15) >> >> I know that this configuration is available from the ILB_BASE_ADDRESS >> (0xfed08000). >> But I don't really understand, how to route the IRQ4 from LPC dev. >> >> Is someone can explain to me how to do it properly? >> >> Many thanks in advance >> Benoit >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot January 2016